Modular solid state power controller with microcontroller

• US 5,752,047 A
• Filed: 07/15/1997
• Issued: 05/12/1998
• Est. Priority Date: 08/11/1995
• Status: Expired due to Term

• Current Assignee: Mcdonnell Douglas Corporation (The Boeing Co.)
• Original Assignee: Mcdonnell Douglas Corporation (The Boeing Co.)
• Inventors: Darty, Mark Anthony, Schwarz, Charles Raymond, Prickett, Guy Brent
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): Seto, Jeffrey K.
• Application Number:
  US08/893,304
• Time in Patent Office: 301 Days
• Field of Search: 395/750.01, 395/750.02, 361/57, 361/79, 361/2
• US Class Current: 713/300
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H01H 2300/03 Application domotique, e.g. for house automation, bus connected switches, sensors, loads or intelligent wiring
• CPC Class Codes: H02H 3/00 Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems H02H7/00; systems for change-over to standby supply H02J9/00 ; integrated protection for motors H02H7/0822
• CPC Class Codes: H02H 3/006 Calibration or setting of parameters
• CPC Class Codes: H02H 3/05 with means for increasing reliability, e.g. redundancy arrangements for logic circuits H03K19/003
• CPC Class Codes: H02J 13/00016 using a wired telecommunication network or a data transmission bus
• CPC Class Codes: H02J 13/00036 the elements or equipment being or involving switches, relays or circuit breakers circuits for indication of single switches H01H9/167
• CPC Class Codes: H02J 13/0004 involved in a protection system
• CPC Class Codes: Y02B 90/20 Smart grids as enabling technology in buildings sector smart grids supporting the management or operation of end-user stationary applications in general, or like technologies with no associated climate change mitigation effect Y04S20/00
• CPC Class Codes: Y02E 60/00 Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
• CPC Class Codes: Y04S 10/20 using protection elements, arrangements or systems
• CPC Class Codes: Y04S 20/14 Protecting elements, switches, relays or circuit breakers
• CPC Class Codes: Y04S 40/124 using wired telecommunication networks or data transmission busses

Abstract

An improved modular solid power controller includes low cost low speed microcomputers embedded within the load cards to control a number of semiconductor power switches associated with corresponding electrical load circuits. A master controller microcomputer on the controller card communicates bilaterally with each of such slave microcomputers via a serial data path that extends along the backplane card and interconnects the former computer with each of the load cards, issuing commands in serial form and in high level language that is received by the addressed slave microprocessor, interpreted and acted upon by controlling the semiconductor power switches associated with the respective slave card.

Claims

1. A modular power controller for selectively controlling the supply of electrical power to a plurality of separate electrical loads, comprising:

master digital microcontroller means, including master program means and memory means containing load command information for each of said electrical loads;

serial data bus means;

said master digital microcontroller means being located at a first location having a first serial output port connected to said serial data bus for selectively issuing load command information in digital serial form onto said serial data bus for each of said plurality of electrical loads;

a plurality of load control means, said load control means being spaced from one another and positioned at other locations spaced from said master controller means;

each said load control means being connected to said serial data bus for receiving said command information;

each of said load control means comprising;

slave microcomputer means, including slave program means;

a plurality of electrical load circuits associated with said microcomputer means;

said slave microcomputer means for receiving said load command information in serial form transmitted by said master digital microcontroller means via said serial bus and processing said received command information, and said slave microcomputer means selectively providing power to respective ones of said plurality of electrical load circuits based upon the processed load command information.

2. The invention as defined in claim 1, wherein said master microcontroller means contains default load control information for each of said load control means;

and wherein said master microcontroller means includes;

second serial output means, and means for assembling and issuing a default load command information for each of said load control means in a serial bit stream via said second serial output means; and

wherein each load control means further includes;

means for extracting and holding said default load control information from said serial bit stream.

3. The invention as defined in claim 2, wherein said means for extracting and holding default load control information from said serial bit stream comprises shift register means;

and

means for connecting said shift register means of all said load control means into a daisy chain connected to said second serial output means of said master digital microcontroller means.

4. The invention as defined in claim 2, further comprising:

second serial bus means; and

wherein said means for extracting and holding load control information comprises serial to parallel shift register means, said shift register means including a register, a serial input, a serial output and a parallel output;

said second serial bus means being coupled to said second serial output port of said master digital microcontroller means and a first of said shift register means for delivering said serial bit stream to a first shift register means; and

daisy chain circuit means connecting a respective serial output of each of said shift register means to a respective serial input of the next adjacent shift register means in said plurality to form a daisy chain of shift registers.

5. The invention as defined in claim 1, wherein each of said load control means includes:

shift register means;

said shift register means including a serial input for receiving digital data input bits, an overflow serial output for outputting digital data bits, and a parallel output for outputting the contents temporarily stored in said shift register means, and clock input for receiving clock pulses to shift said shift register means, whereby digital bits appearing at said input are entered into said register means, bits in said shift register means are serially advanced in position in said shift register means from one stage therein to the next, and digital bits residing in said final stage of said shift register means are advanced out of said serial output at said overflow serial output in response to a clock pulse;

wherein said master microcontroller means includes;

second serial output means; and

clocking means for producing clock pulses to clock out a serial digital data pattern from said second serial output means, one bit at a time;

said master microcontroller means producing a serial bit pattern of digital information comprising a plurality of packets of information for registration of respective packets in corresponding ones of said shift register means with only one of said packets containing a code representative of the default load command information sent by said master microcontroller to the load control means containing said shift register means;

clock bus means for connecting said clocking means in circuit with each of said shift register means to convey clock pulses to said clock input of each of said shift register means;

first lead means for coupling said second serial output means to a shift register means input of a first of said plurality of load control means;

daisy chain lead means for connecting said shift register output of each of said load control means, excepting a last one of said shift register means, to a shift register means serial input of one other load control means on a mutually exclusive basis to interconnect all said shift register means in a daisy chain circuit arrangement;

wherein digital information clocked from said second serial output means is paraded into said shift registers, and wherein said main microcontroller means clocks out a predetermined parade of digital bits to fill all of said shift registers, in response to a predetermined number of clock pulses issued by said main microcontroller means and wherein said digital bits stored thereby in the shift register of a selected one of said load control means selected by said master microcontroller means, upon cessation of said clock pulses, defines, at the parallel output of said selected shift register, a unique pattern of bits representative of said default load command information issued by said master microcontroller to said selected load control means via said serial bus.

6. The invention as defined in claim 5, wherein said parade of bits from said verification means comprises in number a number equal to the number of shift register means multiplied by the number of serial bits that said shift register means is capable of registering.

7. The invention as defined in claim 5 wherein each load control means further comprises a plurality of semiconductor power switch means for controlling power supplied to respective ones of said electrical load circuits in response to commands issued by said slave microcomputer means, the modular power controller further comprising:

a plurality of prioritizing means, one for each of said semiconductor power switch means;

each of said prioritizing means having multiple inputs, with each input being ranked in level of priority from highest priority to lowest priority, and having an output;

said output of each said prioritizing means being connected to an input of a respective one of said semiconductor power switch means;

means for coupling the parallel output of said shift register means to the highest priority input of said prioritizing means in response to a default priority condition;

means connecting the output of said slave microcontroller means to the lowest priority input of said prioritizing means;

watchdog circuit means;

a plurality of gating means, each of said plurality of gating means being associated with a corresponding one of said plurality of semiconductor power switch means;

said watchdog circuit means having an input for receiving load commands issued by said slave microcomputer means and for producing a plurality of digital FALSE outputs responsive to receiving said load commands and producing a plurality of digital TRUE outputs in the absence of said load commands, said plurality of digital outputs corresponding in number to said plurality of gating means;

means coupling each output of said watchdog circuit means to a control input of a corresponding one of said gating means;

a plurality of monitoring means, one of each of said plurality of semiconductor power switch means;

each said monitoring means associated with each of said semiconductor power switch means for producing an output representative of the current conducting state of the associated semiconductor power switch means;

means coupling the output of each said monitoring means to a second input of a corresponding of said gating means;

means coupling said output of said gating means to a greater priority input of said prioritizing means than said output of said slave microcontroller means and lower in priority than said priority input of said shift register means parallel output;

said gating means for outputting the respective input at said second input only in response to a TRUE input at the respective control input, whereby said watchdog circuit means maintains said semiconductor power switch means in its existing conductivity state upon the failure of said slave microcomputer means, overriding any commands thereafter from said slave microcomputer means, in the absence of a default condition and whereby said semiconductor power switch means is set into the default load configuration in response to a default load condition, irrespective of the outputs of either said watchdog circuit means and said slave microcontroller means.

8. The invention as defined in claim 1 wherein each load control means further comprises a plurality of semiconductor power switch means for controlling power supplied to respective ones of said electrical load circuits in response to commands issued by said slave microcomputer means, the modular power controller further comprising:

a plurality of prioritizing means, one for each of said semiconductor power switch means;

each of said prioritizing means having multiple inputs, with each input being ranked in level of priority from highest priority to lowest priority, and having an output;

said output of each said prioritizing means being connected to an input of a respective one of said semiconductor power switch means;

means connecting the output of said slave microcontroller means to the lowest priority input of said prioritizing means;

watchdog circuit means;

a plurality of gating means, each of said plurality of gating means being associated with a corresponding one of said plurality of semiconductor power switch means;

said watchdog circuit means having an input for pulses issued by said slave microcomputer means and for producing a plurality of digital FALSE outputs responsive to receiving said load commands and producing a plurality of digital TRUE outputs in the absence of said pulses for a predetermined period of time, said plurality of digital outputs corresponding in number to said plurality of gating means;

means coupling each output of said watchdog circuit means to a control input of a corresponding one of said gating means;

a plurality of monitoring means, one for each of said plurality of semiconductor power switch means;

each said monitoring means associated with each of said semiconductor power switch means for producing an output representative of the current conducting state of the associated semiconductor power switch means;

means coupling the output of each said monitoring means to a second input of a corresponding of said gating means;

means coupling said output of said gating means to a greater priority input of said prioritizing means than said output of said slave microcontroller means;

said gating means for outputting the respective input at said second input only in response to a TRUE input at the respective control input, whereby said watchdog circuit means maintains said semiconductor power switch means in its existing conductivity state upon the failure of said slave microcomputer means, overriding any commands thereafter from said slave microcomputer means.

9. The invention as defined in claim 1, further comprising:

arc extinguishing means associated with each electrical load circuit;

said arc extinguishing means comprising;

first semiconductor switch means having a control input and an output, said output being connected across said load circuit, said first semiconductor switch means being normally in a non-conductive state and switchable to an electrically conductive state, responsive to a TRUE input applied to said control input of said first semiconductor switch means;

current sensor means for monitoring current flow in said load circuit and providing an output indicative of current level;

second semiconductor switch means, having a control input and an output, said second semiconductor switch means being normally in an electrically conductive state and being switchable to an electrically non-conductive state responsive to a TRUE input applied to said control input of said second semiconductor switch means, said second semiconductor switch means being connected in series with said load circuit;

control circuit means for supplying a TRUE input to said control input of said second semiconductor switch means, responsive to said current sensor means output attaining a predetermined interrupt level;

means for inputting said current sensor means output to said respective slave microcomputer means, wherein said respective slave microcomputer means senses the level of said line current;

voltage sensing means for coupling said load circuit to said respective slave microcomputer means, wherein said respective slave microcomputer means senses the level of said line-voltage;

said slave microcomputer means including program means for detecting the simultaneous presence of low line voltage on said load circuit and a zero line current measured by said current sensor means and for providing a TRUE input to said first semiconductor switch means, whereby said first semiconductor switch means provides a conductive circuit across the lines of said load circuit.

10. The invention as defined in claim 9 further comprising:

analog to digital converter means for converting current levels sensed by said current sensor means and voltage levels sensed by said voltage monitoring means to digital form for respective input to said slave microcomputer means.

11. The invention as defined in claim 1 wherein each load control means further comprises a plurality of semiconductor power switch means for controlling power supplied to respective ones of said electrical load circuits in response to commands issued by said slave microcomputer means, the modular power controller further comprising:

verification means for verifying said load command information received at said load control means prior to selectively individually setting the electrical state of each of said associated semiconductor power switch means in accordance with said load control information.

12. The invention as defined in claim 11, wherein said master digital microcontroller means includes verification serial input means;

and wherein said verification means comprises;

buffer means located at each load control means, each said buffer means for receiving and holding load command information from the associated slave microcontroller means;

register means for receiving a copy of said load command information;

means for copying said load command information into said buffer means;

and means for sending said copy of said load command information to said master digital controller means, wherein said master digital controller means verifies said load command information;

and means for outputting said load command information from said buffer means to said semiconductor power switch means, responsive to said master digital controller verifying said load command information.

13. The invention as defined in claim 1 wherein each load control means further comprises a plurality of semiconductor power switch means for controlling power supplied to respective ones of said electrical load circuits in response to commands issued by said slave microcomputer means,

wherein said master digital microcontroller means includes a verification serial input, a strobe output and a clock output;

wherein said slave microcontroller includes a write command output; and

wherein each said load control means further includes;

shift register means;

first latch means;

second latch means;

said first latch means having an input coupled to said output of said slave microcontroller means for receiving a copy of said load command information and outputting said load control information, responsive to a write command from said slave microcontroller means;

said second latch means having an output connected to said semiconductor power switch means and an input connected to an output of said first latch means for coupling load command information to said semiconductor power switch means, responsive to a strobe signal from said master digital controller means;

means for loading said shift register means with a copy of said load command information from said first latch means, responsive to a load signal from said master digital controller means;

means in said slave microcontroller for supplying a write command following output of said load command information, whereby said load command is entered in said first latch means;

means connecting said shift register means of each of said load control means in a serial chain to said verification serial input of said master microcontroller means, wherein a serial output of one said shift register means is connected to the serial input of the next shift register means in said chain, whereby a serial line of data containing load command information for each of said load control means is formed in response to said load signal from said master digital microcontroller means;

means in said master digital microcontroller means for supplying a load command to each of said power control means, whereby said shift register means are loaded with a copy of load command information;

means in said master microcontroller means for initiating said clock output to supply clock pulses to each of said shift register means, wherein said serial line of data is shifted into said master microcontroller means;

said master microcontroller means further including;

means for comparing load command information received via said verification serial input means with the load command information previously sent to said slave microcontroller means via said serial data bus and, responsive to a match thereof, for providing a strobe output to said second latch means, whereby said load command information is entered into said semiconductor power switch means.

14. In a modular power controller of the type containing a controller card, a plurality of load cards and a backplane card in which each of said controller cards and load cards are interconnected in circuit by means of said backplane card, wherein said modular power controller selectively controls the supply of electrical power to a plurality of separate electrical loads, the improvement therein wherein said controller card issues command information selectively in serial digital form onto said backplane card for each of said load cards;

and wherein each said load card includes a plurality of semiconductor power switches and an embedded microprocessor, said embedded microprocessor for receiving command information in serial form transmitted from said controller card via said backplane card, for interpreting and processing said received command information and for selectively controlling the electrical state of said semiconductor power switches associated therewith responsive to said interpreted processed received information, whereby each load card individually controls a plurality of electrical load circuits.

15. In a modular power controller of the type containing a controller card, a plurality of load cards and a backplane card in which each of said controller cards and load cards are interconnected in circuit by means of said backplane card, wherein said modular power controller selectively controls the supply of electrical power to a plurality of separate electrical loads, the improvement therein wherein said controller card issues command information selectively in serial digital form onto said backplane card for each of said load cards;

and wherein each said load card includes a plurality of semiconductor power switches and an embedded microprocessor, said embedded microprocessor for receiving command information in serial form transmitted from said controller card via said backplane card, for interpreting and processing said received command information and for selectively controlling the electrical state of said semiconductor power switches associated therewith responsive to said interpreted processed received information, whereby each load card individually controls a plurality of electrical load circuits; and

wherein said controller card contains a default command output for providing default command information;

wherein each said load card contains a daisy chain input and a daisy chain output connected respectively to said backplane card; and

wherein said backplane card includes circuit means for connecting said daisy chain input of a first one of said plurality of said load cards to a verify output of said controller card and for connecting said daisy chain input of each of said remaining load cards to said daisy chain output of the respective preceding load card in said daisy chain; and

wherein each said load card further includes;

a plurality of prioritizing means, each said prioritizing means having at least two priority inputs for passing only the signal at the input having the highest priority, each of said plurality of prioritizing means being associated with a respective one of said plurality of semiconductor switch means on said load card;

semiconductor registering means for receiving said command information at said daisy chain input and passing said command information to said daisy chain output, wherein said command information is passed to the next successive load card in said daisy chain, and for outputting said received command information to a first input of each of said plurality of associated comparison means;

each said comparison means having a second of said inputs coupled to an output of said embedded microcontroller for receiving low level command information from said microcontroller;

and wherein each of said plurality of semiconductor switch means on said respective load card being responsive to a TRUE output from an associated one of comparison means for completing an electrical power transmission circuit.

16. The invention as defined in claim 15, wherein said controller card includes:

clock means for providing clock pulses;

clock bus means wired between said controller card and each of said load cards to provide verify clock pulses to each of said load cards;

and wherein said semiconductor verifying means comprises;

serial to parallel shift register means;

said shift register means having a serial input connected to said verify input of said load card;

a clock input connected to said verify clock bus for shifting data into and serially advancing data through said shift register in response to clock pulses;

a serial output connected to said verify output of said load card for outputting data bits shifted through said shift register responsive to successive clock pulses, and a parallel output for outputting the contents of said shift register in parallel form;

and wherein said parallel output of said shift register means is connected to said first input of said comparison means.

17. The invention as defined in claim 15, wherein said embedded microcontroller on each load card further includes means for compiling and transmitting a report of the electrical status of said load card in serial form via said backplane card to said controller card;

and wherein said controller card includes means for receiving and assessing said electrical status information.

18. The invention as defined in claim 17, wherein said electrical includes status of electrical arcing.

19. The invention as defined in claim 15, further including latch circuit means for preventing change of state of said semiconductor switch means responsive to withdrawal of electrical power.

20. The invention as defined in claim 15 wherein said controller card includes microprocessor means, shadow microprocessor means, and means for detecting disablement of said microprocessor means, said shadow microprocessor means performing identical functions to said microprocessor means and providing output to replace output from said microprocessor means only in the event of detection of disablement of said microprocessor means.

21. The invention as defined in claim 20, further comprising:

first power source means for providing electrical to said microprocessor means; and

back up power source means for providing alternate electrical power to said microprocessor means only in the event of failure of said first power supply means.

22. In a modular solid state power controller of the type containing:

a panel;

said panel containing;

first coupling means for coupling to an external electrical power source,

second coupling means for coupling electrical power to a plurality of electrical loads and

input coupling means for receiving electrical data from an external source;

a first circuit board;

said first circuit board containing a master digital microcontroller, said digital microcontroller having an input coupled to said input coupling means for receiving and processing said electrical data;

a plurality of slave circuit boards, each said slave circuit boards containing switching means for controlling the flow of electrical power in a respective plurality of electrical load circuits between an on and an off state;

a backplane circuit board;

said backplane circuit board containing a plurality of electrical connector means, first electrical transmission paths for interconnecting signals from said master microcontroller and said slave circuit cards and second electrical transmission paths for interconnecting electrical power between said respective slave circuit boards and said second coupling means of said panel, said second electrical transmission paths comprising a plurality of individual transmission paths;

said panel, first circuit board and said slave circuit board being oriented in spaced parallel relationship and orthogonal to said backplane circuit board;

each of said first circuit board and said slave circuit boards containing electrical connector means for mating engagement with a mating electrical connector means on said backplane circuit board, wherein said first electrical transmission paths is connected amongst all said circuit boards and wherein said second electrical transmission path is connected amongst all said slave circuit boards and said second coupling means of said panel;

the improvement

wherein said power switching means comprises semiconductor switch means, said semiconductor switch means having a control input and being switchable between electrical conducting and non-conducting states in dependence upon a control signal applied to said control input;

wherein said master microcontroller means includes means for issuing command signals in serial digital form and applying same to said first electrical transmission path of said backplane circuit board responsive to said data information;

and wherein each of said slave circuit boards further contains slave microcontroller means having an output coupled to said control input of said semiconductor switch means for receiving said command signals in serial form via said first electrical transmission path and processing said command signals to low level command signals applied to said output for controlling the electrical state of said semiconductor switch means.

23. The invention as defined in claim 22, wherein said semiconductor switch means comprises a plurality of individual semiconductor switches;

and wherein said output of said slave microcontroller means comprises a plurality of outputs with one output for each of said semiconductor switches, whereby said semiconductor switches are individually controlled by said slave microcontroller.

24. A power controller comprising:

master digital microcontroller means, including program means;

a plurality of N load control means, each load control means including a programmed digital slave microcomputer means; and

a plurality of Y semiconductor power switches associated with said programmed digital microcomputer means, each of said semiconductor power switches being configurable between at least two modes of operation;

a serial data bus, said serial data bus coupled between said master digital microcontroller means and said N load control means to provide a digital communication path therebetween;

each said programmed digital slave microcomputer means having a communications port connected to said serial data bus;

said master digital microcontroller means containing load configuration information for each of said Y power semiconductor switches on each of said N load control means and address information for each of said N load control means, and having a first serial output for outputting addressed load configuration command information in digital serial form onto said serial data bus for communication to a respective addressed digital slave microcomputer in a selected load control means, whereby each of said N load control means selectively receives load configuration command information from said master microcontroller via said serial bus;

said master digital microcontroller means further having a second serial output;

a plurality of N serial to parallel shift registers, each having a serial input, a serial output and an inhibit input;

each of said shift registers being associated with a corresponding one of said load control means;

daisy chain circuit means coupling said second serial output port of said master digital microcontroller means and said serial inputs and serial outputs of each of said N shift registers in a daisy chain, wherein digital bits outputted from said second serial output port is inputted into a first shift register means in said daisy chain and digital bits outputted from a serial output of one shift register means is inputted to the next shifter register means in said daisy chain;

said master microcontroller including program means for selectively assembling packets of load configuration information for each of said N load control means in the form of data bits and assembling the first through Nth packets of data bits in reverse serial order to form a stream of digital bits with the Nth packet for said Nth shift register means being arranged first in said stream and said 1st data packet for the 1st shift register means in said daisy chain arranged last in said stream and outputting said stream of bits from said second serial port, whereby each of said N shift register means respectively receives and registers specified load configuration information and outputs the registered load configuration information at its respective parallel output;

each said load control means, further including;

prioritizing gate means having a plurality of priority level inputs between at least first and second priority levels for outputting only the data present on the higher priority level input;

said parallel output of said associated shift register means being connected to said first level priority input of said prioritizing gate means and load configuration command information from an output of said associated slave microcomputer means being connected to said second level priority input of said prioritizing gate means, whereby said Y semiconductor power switch means is set to the configuration specified by the load configuration command information from the higher level input.

25. The invention as defined in claim 24, further comprising:

selectively operable inhibit switch means for preventing additional inputs to said serial inputs of each of said shift register means to prevent change in load configuration information at the respective parallel output of each of said shift register means.

26. The invention as defined in claim 25, wherein said master microcontroller means includes a third output port;

means for coupling said third serial input port to said shift register means output of said Nth shift register means; and

wherein said master microcontroller includes program means for providing a predetermined number of digital bits at said second output of said master microcontroller means to parade load configuration information in said shift register means into said master microcontroller means and for comparing the load configuration information in said parade with load configuration information retained in said master microcontroller means.

27. A computerized arc extinguishing circuit for an electrical load circuit comprising:

arc extinguishing means associated with said electrical load circuit;

said arc extinguishing means comprising;

first semiconductor switch means having a control input a nd an output, said output being connected across said load circuit, said first semiconductor switch means being normally in a non-conductive state and switchable to an electrically conductive state, responsive to a TRUE input applied to said control input of said first semiconductor switch means;

current sensor means for monitoring current flow in said load circuit and providing an output indicative of current level;

second semiconductor switch means, having a control input and an output, said second semiconductor switch means being normally in an electrically conductive state and being switchable to an electrically non-conductive state responsive to a TRUE input applied to said control input of said second semiconductor switch means, said second semiconductor switch means being connected in series with said load circuit;

control circuit means for supplying a TRUE input to said control input of said second semiconductor switch means, responsive to said current sensor means output attaining a predetermined interrupt level;

microcomputer means, including program means for detecting the simultaneous presence of a low line voltage on said load circuit and a zero line current measured by said current sensor means and for providing a TRUE input to said first semiconductor switch means, whereby said first semiconductor switch means provides a conductive circuit across the lines of said load circuit;

means for inputting said current sensor means output to said microcomputer means, wherein said microcomputer means senses the level of said line current; and

voltage sensing means for coupling said load circuit to said microcomputer means, wherein said microcomputer means senses the level of said line voltage.

28. The invention as defined in claim 27, further comprising:

analog to digital converter means for converting current levels sensed by said current sensor means and voltage levels sensed by said voltage monitoring means to digital form for respective input to said microcomputer means.