Write inhibited registers

• US 5,752,063 A
• Filed: 12/19/1995
• Issued: 05/12/1998
• Est. Priority Date: 12/08/1993
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Packard Bell NEC
• Inventors: Nicol, Mark D., DeLisle, David J., Krau, Michael P., Fakhruddin, Saifuddin, Gauthier, Lloyd W., Kohtz, Robert A., DeRoo, David T.
• Primary Examiner(s): Geckil, Mehmet B.
• Application Number:
  US08/575,004
• Time in Patent Office: 875 Days
• Field of Search: 395/800, 395/700, 395/289, 395/830, 395/828
• US Class Current: 712/38
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/32 Address formation of the next instruction, e.g. by incrementing the instruction counter G06F9/38 takes precedence
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

The invention provides a simple I/O port which can be used to support a variety of system functions such as a revision, configuration or identification register. This port is provided with a means to be programmable once, upon system power-up so that changes to the port contents are possible, but only under controlled conditions. Once the register has been programmed, it will no longer respond to writes.

Claims

1. A computer system including a data bus, an address bus, a control bus and a central processing unit (CPU) coupled to said address bus, said data bus and said control bus, for generating data signals on said data bus, address signals on said address bus and control signals including read signals and write signals on said control bus, said system comprising:

a first hardware register having a first predetermined address, coupled to the data bus and the address bus, for storing data in response to a predetermined control signal;

a decoder, coupled to the address bus, for generating a predetermined decode signal when said first predetermined address is on the address bus; and

means responsive to the write signal and said predetermined decode signal for generating said predetermined control signal and enabling data to be stored in said first hardware register once anytime after the computer system is powered up, the first time the CPU writes to said first hardware register after the computer system is powered up and subsequently automatically inhibiting in hardware, data from being stored and altered in said first hardware register until the computer system is powered up again, said first hardware register including a data input and a clock input and said qenerating means including a predetermined gate coupled to said clock input, said predetermined gate only enabled for the first write to said first hardware register and subsequently disabled.

2. The computer system as recited in claim 1, wherein said CPU has at least two modes of operation including a real mode of operation for accessing memory up to one megabyte and a mode of operation for accessing memory above one megabyte adapted to be selected by one or more predetermined control signals;

and said computer system further including;

means for enabling said mode of operation for memory accesses over one megabyte in response to a hardware based control signal; and

a system control processor (SCP) coupled to the bus and generating a read signal, a write signal and address signals on the bus and a reset signal for resetting the CPU.