Mesh parallel computer architecture apparatus and associated methods
First Claim
1. Digital data processing apparatus for synchronously processing data from a host computer, comprising:
- program memory means for storing data, and bus means connecting said program memory means to the host computer;
a master processor element and an array of slave processor elements, said master processor element having means to access said data within said program memory and for broadcasting instructions to said array; and
input/output module means connected to communicate with said bus means and having a plurality of data links connected to said array, each of said data links providing serial communication with selected slave processor elements;
wherein each of said slave processor elements comprises(i) an input/output processor section having interprocessor communication links for communicating data to and from selected other processor elements within said array, and further having means for communicating data to and from said input/output module means,(ii) internal memory means having a storage capacity of at least 128 kilobytes for storing executable code, and (iii) a core processor section for processing said executable code and said instructions, each of said processor sections being operable independently from the other of said processor sections;
said slave processor elements synchronously executing at least one of said instructions and said executable code at a throughput rate of at least 120 MFLOPS.
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Abstract
A Monolithic Synchronous Processor (MeshSP) processes data and incorporates a mesh parallel computer architecture, primarily SIMD, thereby combining high data throughput with modest size, weight, power and cost. Each MeshSP processor node utilizes a single DSP processor element, a large internal memory of at least 128k-bytes, and separately operable computational and I/O processing sections. The processor element provides data throughput of at least 120 MFlops. The processor is programmed in ANSI C and without parallel extensions. A combination of on-chip DMA hardware and system software simplifies data I/O and interprocessor communication. The MeshSP is programmed to solve a wide variety of computationally demanding signal processing problems. A functional simulator enables MeshSP algorithms to be coded and tested on a personal computer.
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Citations
20 Claims
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1. Digital data processing apparatus for synchronously processing data from a host computer, comprising:
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program memory means for storing data, and bus means connecting said program memory means to the host computer; a master processor element and an array of slave processor elements, said master processor element having means to access said data within said program memory and for broadcasting instructions to said array; and input/output module means connected to communicate with said bus means and having a plurality of data links connected to said array, each of said data links providing serial communication with selected slave processor elements; wherein each of said slave processor elements comprises (i) an input/output processor section having interprocessor communication links for communicating data to and from selected other processor elements within said array, and further having means for communicating data to and from said input/output module means, (ii) internal memory means having a storage capacity of at least 128 kilobytes for storing executable code, and (iii) a core processor section for processing said executable code and said instructions, each of said processor sections being operable independently from the other of said processor sections; said slave processor elements synchronously executing at least one of said instructions and said executable code at a throughput rate of at least 120 MFLOPS.
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2. A monolithic processor element comprising:
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memory; an external port for receiving instructions; a core processor for processing instructions received through the external port; a set of selectable link ports; an input/output register set for holding data transferred between memory and the selectable link ports and transferred between selectable link ports; a bus system for transfer of data between the core processor and memory and between the input/output register set and memory; and an I/O controller which, for successive data elements, performs a direct memory access to read the data elements from memory to the input/output register set, and after a programmable number of cycles of data transfers between selectable ports through the input/output register set, performs a direct memory access to write the data elements from the input/output register set to memory. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10)
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11. A digital data processing apparatus for synchronously processing data from a host computer, comprising:
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a program memory for storing data; a bus connecting the program memory to the host computer; a master processor element and an array of slave processor elements, the master processor element having means to access said data within said program memory and for broadcasting instructions to said array; and an input/output module connected to communicate with the bus and having a plurality of data links connected to the array, each of the data links providing serial communication with selected slave processor elements; wherein each of the slave processor elements comprises (i) slave memory and an external port for receiving instructions; (ii) a core processor for processing instructions received through the external port; (iii) a set of selectable link ports; (iv) an input/output register set for holding data transferred between slave memory and the selectable link ports and transferred between selectable link ports; (v) a bus system for transfer of data between the core processor and slave memory, and between the input/output register set and slave memory; and (vi) an I/O controller which, for successive data elements, performs a direct memory access to read the data elements from slave memory to the input/output register set, and after a programmable number of cycles of data transfers between selectable ports through the input/output register set, performs a direct memory access to write the data elements from the input/output register set to slave memory. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A method for transferring data to selected processor elements in a synchronous digital data processing system, comprising the steps of:
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processing instructions received through the external port in a core processor; storing data transferred between memory and selectable link ports and transferred between selectable link ports in an input/output register set; transferring data between the core processor and memory and between the input/output register set and memory over a bus system; performing, for successive data elements, a direct memory access to read the data elements from memory to the input/output register set; and performing, after a programmable number of cycles of data transfers between selectable ports through the input/output register set, a direct memory access to write the data elements from the input/output register set to memory.
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Specification