Surface mount and flip chip technology for total integrated circuit isolation

• US 5,753,529 A
• Filed: 05/19/1995
• Issued: 05/19/1998
• Est. Priority Date: 05/05/1994
• Status: Expired due to Fees

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, Ho, Yueh-Se, Owyang, King, Chang, Mike F., Dun, Jowei
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/444,660
• Time in Patent Office: 1,096 Days
• Field of Search: 437/67, 437/68, 437/61, 437/209, 437/226, 437/902, 437/974, 148/DIG. 135
• US Class Current: 438/118
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/3738 Semiconductor materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: Y10S 148/135 Removal of substrate
• CPC Class Codes: Y10S 438/928 Front and rear surface processing
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

Claims

1. A method of forming an integrated circuit, comprising the steps of:

providing a semiconductor substrate having a principal surface;

forming a plurality of semiconductor devices in the substrate;

forming a plurality of trenches in the substrate extending from the principal surface thereof into the substrate to a particular depth;

forming a layer of insulating material in each of the trenches;

forming a pattern of conductive lines overlying the principal surface and in electrical contact with the devices;

bonding a thermal conductive plate to the substrate and overlying the principal surface thereof; and

removing a portion of the substrate from a backside surface thereof opposing the principal surface, thereby exposing at least a bottom part of each of the trenches.

2. The method of claim 1, further comprising the steps of:

forming a conductive layer on the backside surface; and

patterning the conductive layer into a plurality of contact regions, each contact region being in contact with a selected portion of the backside surface as defined by the plurality of trenches.

3. The method of claim 1 wherein the step of removing leaves a remaining thickness of the substrate of less than about 300 μ

m.

4. The method of claim 1, further comprising the step of forming a second pattern of conductive lines on a surface of the plate prior to the step of bonding;

wherein the step of bonding comprises electrically contacting portions of the second pattern to portion s of the first pattern.

5. The method of claim 1, further comprising the step of forming a protective layer overlying the substrate prior to the step of bonding;

wherein the step of bonding comprises applying an adhesive to the protective layer.

6. The method of claim 1, further comprising the steps of:

forming a plurality of vias extending from the backside surface to the principal surface of the substrate, after the step of removing;

providing conductive material in each of the vias, the conductive material in each via being in electrical contact on the principal surface with a portion of the pattern of conductive lines, and the conductive material in each via forming an electrical contact on the backside surface.

7. The method of claim 6, wherein the step of providing conductive material comprises forming a layer of the conductive material on the backside surface, and further comprising:

forming the layer of conductive material into a plurality of posts extending outward from the backside surface, each post being electrically connected to the conductive material in one of the vias.