Static-induction transistors having heterojunction gates and methods of forming same

• US 5,753,938 A
• Filed: 08/08/1996
• Issued: 05/19/1998
• Est. Priority Date: 08/08/1996
• Status: Expired due to Fees

• Current Assignee: North Carolina State University (University of North Carolina System)
• Original Assignee: North Carolina State University (University of North Carolina System)
• Inventors: Shenoy, Praveen Muraleedharan, Baliga, Bantval Jyant, Thapar, Naresh I.
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US08/694,276
• Time in Patent Office: 649 Days
• Field of Search: 257/77, 257/136, 257/192, 257/264, 257/266, 257/267
• US Class Current: 257/77
• CPC Class Codes: H01L 29/7392 with PN junction gate, e.g. field controlled thyristors (FCTh), static induction thyristors (SITh)
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT

Abstract

A semiconductor switching device includes a plurality of adjacent heterojunction-gate static-induction transistor (SIT) unit cells connected in parallel in a monocrystalline silicon carbide substrate having first and second opposing faces, a relatively highly doped silicon carbide drain region adjacent the first face and a relatively highly doped silicon carbide source region adjacent the second face. A relatively lightly doped drift region is also provided in the substrate and extends between the drain region and source region. A plurality of trenches are also provided in the substrate so that sidewalls of the trenches extend adjacent the drift region. Each trench preferably contains a relatively highly doped second conductivity type nonmonocrystalline silicon gate region comprised of a material selected from the group consisting of polycrystalline silicon or amorphous silicon. These gate regions form P-N heterojunctions with the drift region at the sidewalls and bottoms of the trenches. An electrically insulating layer, such as a thermally grown silicon dioxide layer, is also provided on the nonmonocrystalline silicon gate regions in order to electrically insulate the gate regions from metallization on the second face. The use of nonmonocrystalline materials for the gate regions is preferred because the nonmonocrystalline lattice structure of the gate regions provides numerous grain boundaries and other lattice defects which act as scattering sites for electrons. By providing scattering sites, the probability that accelerated electrons will reach the threshold energy to induce avalanche breakdown in the gate regions is reduced and an increase in forward blocking voltage capability is achieved. Hole injection from the P+ polycrystalline silicon gate region into the N-type drift can also be suppressed to significantly improve the switching speed by reducing the amount of stored charge in the drift region.

Claims

1. A heterojunction-gate static-induction transistor, comprising:

a monocrystalline silicon carbide substrate having first and second opposing faces thereon and containing therein a silicon carbide drain region of first or second conductivity type adjacent the first face, a silicon carbide source region of first conductivity type adjacent the second face and a silicon carbide drift region of first conductivity type between said silicon carbide source and drain regions, said silicon carbide drift region having a lower first conductivity type doping concentration therein than said silicon carbide source region;

a first trench in said silicon carbide substrate at the second face, said first trench having a first sidewall extending adjacent said silicon carbide drift region;

a first nonmonocrystalline silicon gate region of second conductivity type in said first trench, said first nonmonocrystalline silicon gate region forming a P-N heterojunction with said silicon carbide drift region at the first sidewall of said first trench;

source and drain electrodes ohmically contacting said source and drain regions, respectively; and

a thermally grown silicon dioxide insulating region in said first trench, between said first nonmonocrystalline silicon gate region and said source electrode;

wherein a first conductivity type doping concentration in said silicon carbide drift region is less than about 5×

10¹⁶ cm^-3 and wherein a second conductivity type doping concentration in said first nonmonocrystalline silicon gate region is greater than about 5×

10¹⁸ cm^-3 ; and

wherein said thermally grown silicon dioxide insulating region comprises second conductivity type dopants therein.

2. An integrated silicon carbide switching device, comprising:

a silicon carbide substrate having first and second opposing faces thereon;

a silicon carbide drain region of first or second conductivity type in said silicon carbide substrate, adjacent the first face;

a silicon carbide source region of first conductivity type in said silicon carbide substrate, adjacent the second face;

a silicon carbide drift region of first conductivity type in said silicon carbide substrate said silicon carbide drift region extending between said silicon carbide source and drain regions;

a plurality of spaced trenches in said silicon carbide substrate at the second face, said trenches having respective sidewalls extending adjacent said silicon carbide drift region;

a nonmonocrystalline silicon gate region of second conductivity type in each of said plurality of spaced trenches, said nonmonocrystalline silicon gate regions forming respective P-N heterojunctions with said silicon carbide drift region at the sidewalls of said plurality of spaced trenches and comprising a material which is selected from the group consisting of amorphous silicon and polycrystalline silicon;

source and drain electrodes ohmically contacting said source and drain regions, respectively; and

a thermally grown silicon dioxide insulating region in each of said plurality of trenches, said thermally grown silicon dioxide regions extending between respective nonmonocrystalline silicon gate regions and said source electrode;

wherein a potential barrier for second conductivity type charge carriers at the P-N heterojunctions is greater than a potential barrier for first conductivity type charge carriers by more than about 0.5 eV; and

wherein said thermally grown silicon dioxide insulating region comprises second conductivity type dopants therein.

3. A silicon carbide static-induction transistor, comprising:

a 4H or 6H monocrystalline silicon carbide substrate having first and second opposing faces thereon and containing therein a silicon carbide drain region of first or second conductivity type adjacent the first face, a silicon carbide source region of first conductivity type adjacent the second face and a silicon carbide drift region of first conductivity type between said source and drain regions, said drift region having a lower first conductivity type doping concentration therein than said source region;

a trench in said silicon carbide substrate at the second face, said trench having a sidewall extending adjacent said drift region; and

a gate region of second conductivity type in said trench, said gate region comprising 3C nonmonocrystalline silicon carbide and forming a P-N junction with said drift region at the sidewall of said trench.

4. The static-induction transistor of claim 3, wherein a potential barrier for second conductivity type charge carriers at the P-N junction is greater than a potential barrier for first conductivity type charge carriers by more than about 0.5 eV.

5. The static-induction transistor of claim 4, further comprising source and drain electrodes ohmically contacting said source and drain regions, respectively;

and polyimide in said trench, between said gate region and said source electrode.