MOS device having a gate to body connection with a body injection current limiting feature for use on silicon on insulator substrates

• US 5,753,955 A
• Filed: 12/19/1996
• Issued: 05/19/1998
• Est. Priority Date: 12/19/1996
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Fechner, Paul S.
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US08/770,616
• Time in Patent Office: 516 Days
• Field of Search: 257/347, 257/350, 257/471, 257/481
• US Class Current: 257/347
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A MOS transistor formed in a silicon on insulator structure includes a rectifying connection between a body portion and the gate. The connection decreases the threshold voltage of the transistor in the reverse bias state and limits a difference in voltage between the body and gate in the forward bias state of the rectifying contact.

Claims

1. A MOS transistor comprising:

a silicon substrate;

an insulative layer formed on said silicon substrate;

a thin layer of lightly doped silicon of a first conductivity type formed on said insulative layer;

said thin layer of silicon having source and drain regions of a second conductivity type formed therein and extending down to said insulative layer;

a body portion of said thin layer of silicon separating said source region and said drain region;

a gate overlying said body portion; and

a rectifying connection between said body portion and said gate to reduce a threshold voltage of said transistor while limiting a gate current to a first level when said transistor is turned on and limiting a voltage difference between said body and said gate when said transistor is turned off.

2. The MOS transistor of claim 1 wherein said rectifying connection comprises a silicide connected to said lightly doped silicon.

3. The MOS transistor of claim 1 wherein said rectifying connection is a schottky diode.

4. The MOS transistor of claim 2 wherein said silicide comprises titanium silicide and said difference in voltage is less than 0.5 volts.

5. A MOS transistor comprising:

a silicon substrate;

an insulative layer formed on said silicon substrate;

a thin layer of lightly doped silicon of a first conductivity type formed on said insulative layer;

said thin layer of silicon having a source region and a drain region of a second conductivity type formed therein;

a body portion of said thin layer of silicon separating said source region and said drain region;

a gate overlying said body portion; and

a rectifying connection between said body portion and said gate, said rectifying connection having a reverse resistance to limit a gate current to a first value when said transistor is turned on and a forward resistance to limit a voltage difference between said body and said gate when said transistor is turned off.

6. The MOS transistor of claim 5 wherein said rectifying connection comprises a silicide connected to said lightly doped silicon.

7. The MOS transistor of claim 5 wherein said rectifying connection is a schottky diode.

8. The MOS transistor of claim 6 wherein said silicide comprises titanium silicide and said difference in voltage is less than 0.5 volts.

9. The MOS transistor of claim 5 wherein said reverse resistance is in the range of 10⁶ to 10¹² ohms.