Video decoder capable of controlling encoded video data

• US 5,754,241 A
• Filed: 11/14/1995
• Issued: 05/19/1998
• Est. Priority Date: 11/18/1994
• Status: Expired due to Term

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Tanahashi, Naoki, Kawahara, Keita, Okada, Shigeyuki, Nakashima, Hayato
• Primary Examiner(s): Au, Amelia
• Assistant Examiner(s): Le, Vu
• Application Number:
  US08/557,615
• Time in Patent Office: 917 Days
• Field of Search: 348/419, 348/405, 348/409, 348/412, 348/415, 348/402, 348/411, 348/390, 348/384, 348/699, 348/416, 348/413, 386/6-8, 386/68, 360/8
• US Class Current: 375/240.05
• CPC Class Codes: H04N 19/132 Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
• CPC Class Codes: H04N 19/14 Coding unit complexity, e.g. amount of activity or edge presence estimation H04N19/146 takes precedence
• CPC Class Codes: H04N 19/146 Data rate or code amount at the encoder output
• CPC Class Codes: H04N 19/152 by measuring the fullness of the transmission buffer
• CPC Class Codes: H04N 19/159 Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
• CPC Class Codes: H04N 19/172 the region being a picture, frame or field
• CPC Class Codes: H04N 19/184 the unit being bits, e.g. of the compressed video stream
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/50 using predictive coding H04N19/61 takes precedence
• CPC Class Codes: H04N 19/587 involving temporal sub-sampling or interpolation, e.g. decimation or subsequent interpolation of pictures in a video sequence
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

An MPEG video decoder capable of preventing a buffer for storing a video stream from overflowing and/or underflowing. The video decoding apparatus decodes a coded video bit stream including a series of pictures to produce decoded pictures. The video decoding apparatus includes: a bit buffer for temporarily storing the video bit stream, a decoding circuit for receiving the video bit stream output from the bit buffer and decoding the video bit stream to produce decoded pictures, and a video bit stream control circuit for controlling an amount of the video bit stream to be supplied to the decoding circuit from the bit buffer based on an amount of data of the video bit stream stored in the bit buffer.

Claims

1. A video decoding apparatus for decoding a coded video bit stream including a series of pictures to produce decoded pictures, said apparatus having a plurality of playback modes, comprising:

a bit buffer for temporarily storing all of said video bit stream regardless of the playback mode;

a decoding circuit for receiving an amount of said video bit stream output from said bit buffer up to a threshold value and decoding said video bit stream to produce said decoded pictures; and

a video bit stream control circuit, operatively connected to said bit buffer and said decoding circuit, for controlling an amount of all of said video bit stream to be supplied to said decoding circuit from said bit buffer based on an amount of data of all of said video bit stream stored in said bit buffer,

wherein said control circuit determines whether an amount of data stored in said bit buffer exceeds the threshold value, the threshold value being predetermined as an amount of said video bit stream which can be safely stored in said bit buffer, and

wherein said control circuit operates to skip a portion of all of said video bit stream in order to prevent the portion of all of said video bit stream from being supplied to said decoding circuit from said bit buffer as long as the amount of data stored in said bit buffer exceeds the threshold value.

2. The video decoding apparatus according to claim 1, wherein said video bit stream control circuit changes said threshold value in proportion to a playback speed for said decoded pictures.

3. The video decoding apparatus according to claim 2, wherein said video bit stream control circuit operates to skip a portion of said video bit stream in a picture by picture manner, as long as the amount of data stored in said bit buffer exceeds said threshold value.

4. The video decoding apparatus according to claim 2, wherein said video bit stream control circuit changes said threshold value based upon a video buffering verifier (VBV) buffer size, a bit rate and a picture rate which are defined by a sequence header included in said video bit stream, and based upon a magnification of an actual playback speed for a normal playback speed.

5. A video decoding apparatus for decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture and a B-picture to produce decoded pictures, comprising:

a bit buffer for temporarily storing said video bit stream;

a decoding circuit for receiving said video bit stream output from said bit buffer and decoding said video bit stream to produce said decoded pictures; and

a video bit stream control circuit, operatively connected to said bit buffer and said decoding circuit, for controlling an amount of said video bit stream to be supplied to said decoding circuit from said bit buffer based on an amount of data of said video bit stream stored in said bit buffer,

wherein said control circuit

determines whether an amount of data stored in said bit buffer exceeds a first threshold value that is predetermined as an amount of said video bit stream which can be safely stored in said bit buffer, said control circuit further operates to change said first threshold value in proportion to a playback speed of said decoded pictures, and

wherein said control circuit operates to allow said video bit stream of said I-picture and said P-picture to be supplied to said decoding circuit, and operates to skip said video bit stream of said B-picture in order to prevent said video bit stream of said B-picture from being supplied to said decoding circuit from said bit buffer as long as the amount of data stored in said bit buffer exceeds said first threshold value.

6. The video decoding apparatus according to claim 5,

wherein said video bit stream control circuit skips said video bit stream of said B-picture to be supplied next, even when an amount of data of said video bit stream stored in said bit buffer is smaller than said first threshold value, after said video bit stream of said I-picture or said P-picture is supplied to said decoding circuit from said bit buffer.

7. The video decoding apparatus according to claim 5,

wherein said determining means determines whether the amount of data stored in said bit buffer exceeds the first threshold value and a second threshold value higher than the first threshold value, and

wherein said video bit stream control circuit skips said video bit stream of said B-picture when the amount of data stored in said bit buffer exceeds said first threshold value, after said video bit stream of said I-picture or said P-picture is supplied to said decoding circuit, and skips said video bit stream of said B-picture when the amount of data stored in said bit buffer exceeds said second threshold value, after said video bit stream of said P-picture is supplied to said decoding circuit.

8. The video decoding apparatus according to claim 7,

wherein said video bit stream control circuit changes said first and second threshold values based upon a video buffering verifier (VBV) buffer size, a bit rate and a picture rate which are defined by a sequence header included in said video bit stream, and based upon a magnification of an actual playback speed for a normal playback speed.

9. A video decoding apparatus for decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture and a B-picture to produce decoded pictures, comprising:

a video bit stream analyzer for determining a picture type for each picture included in said video bit stream and analyzing an amount of data of said video bit stream picture by picture;

a bit buffer for temporarily storing said video bit stream from said video bit stream analyzer;

a decoding circuit for receiving said video bit stream output from said bit buffer and decoding said video bit stream to produce decoded pictures; and

a video bit stream control circuit, operatively connected to said bit buffer and said decoding circuit, for controlling an amount of said video bit stream to be supplied to said decoding circuit from said bit buffer based upon an amount of data of said video bit stream stored in said bit buffer,

wherein said control circuit determines whether an amount of data stored in said bit buffer exceeds a threshold value that is predetermined as an amount of said video bit stream which can be safely stored in said bit buffer, said control circuit further operates to change said threshold value in proportion to a playback speed of said decoded pictures, and

wherein, when said control circuit determines that the amount of data stored in said bit buffer exceeds the threshold value, said control circuit operates to selectively skip a portion of said, video bit stream in a picture by picture manner in order to prevent said video bit stream from being supplied to said decoding circuit from said bit buffer, and the portion to be skipped is selected based upon the picture type for each picture and the amount of data for each picture, detected by said video bit stream analyzer.

10. The video decoding apparatus according to claim 9, wherein said video bit stream control circuit changes said threshold values based upon a video buffering verifier (VBV) buffer size, a bit rate and a picture rate which are defined by a sequence header included in said video bit stream, and based upon a magnification of an actual playback speed for a normal playback speed.

11. A video decoding apparatus for decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture and a B-picture to produce decoded pictures, comprising:

a bit buffer for temporarily storing said video bit stream, said bit buffer having a capacity defined by adding a value obtained by dividing a bit rate by a picture rate to a video buffering verifier (VBV) buffer size;

a decoding circuit for receiving said video bit stream output from said bit buffer and decoding said video bit stream to produce said decoded pictures; and

a video bit stream control circuit, operatively connected to said bit buffer and said decoding circuit, for controlling an amount of said video bit stream to be supplied to said decoding circuit from said bit buffer based on an amount of data of said video bit stream stored in said bit buffer,

wherein said control circuit determines whether an amount of data stored in said bit buffer exceeds a first threshold value indicative of said VBV buffer size and a second threshold value indicative of a value obtained by adding a value resulting from division of said bit rate by said picture rate to said VBV buffer size,

wherein said control circuit operates to allow said video bit streams of said I-picture and said P-picture to be supplied to said decoding circuit, and operates to skip said video bit stream of said B-picture in order to prevent said video bit stream of said B-picture from being supplied to said decoding circuit from said bit buffer as long as the amount of data of stored in said bit buffer lies between said first threshold value and said second threshold value, and further operates to skip a portion of said video bit stream regardless of a type of a picture as long as said amount of data stored in said bit buffer exceeds said second threshold value.

12. The video decoding apparatus according to claim 11, said video bit stream control circuit further comprising:

a picture header detector for determining a picture type for a picture based on a picture header included in said video bit stream output from said bit buffer.

13. The video decoding apparatus according to claim 11, wherein said bit buffer has a capacity defined by adding a value, obtained by dividing said bit rate by said picture rate, and a margin value to said VBV buffer size.

14. A video decoding apparatus for decoding a coded video bit stream including a series of pictures to produce decoded pictures, said apparatus having a plurality of playback modes, comprising;

a bit buffer for temporarily storing all of said video bit stream regardless of the playback mode;

a decoding circuit for receiving said video bit stream output from said bit buffer and decoding said video bit stream to produce said decoded pictures; and

an operation control circuit for controlling a reading operation of said bit buffer and a decoding operation of said decoding circuit based on an amount of data of said video bit stream stored in said bit buffer being less than a threshold value that is predetermined as an amount of said video bit stream and indicates a possibility of an underflow of said bit buffer, wherein said operation control circuit operates to inhibit said reading operation of said bit buffer and said decoding operation of said decoding circuit when the amount of data is less than the threshold value in order to supply already-decoded pictures to said bit buffer during a period from a point of time at which an underflow of said bit buffer has occurred to a point of time at which the underflow is released.

15. The video decoding apparatus according to claim 14,

wherein said operation control circuit determines whether the amount of data stored in said bit buffer is less than the threshold value, wherein said operation control circuit operates to inhibit said reading operation of said bit buffer and said decoding operation of said decoding circuit in order to supply the already-decoded pictures so long as the amount of data stored in said bit buffer is smaller than said threshold value.

16. The video decoding apparatus according to claim 15, wherein said threshold value is set to a value obtained by multiplying said bit rate by a video buffering verifier (VBV) delay value.

17. The video decoding apparatus according to claim 14, wherein said pictures include an I-picture, a P-picture and a B-picture, said operation control circuit determines a picture type for a picture based on a picture header included in said video bit stream output from said bit buffer, and, when said underflow of said bit buffer has occurred during decoding of said B-picture, said operation control circuit skips a remaining portion of said video bit stream of B-picture and continues decoding.

18. The video decoding apparatus according to claim 14, wherein said pictures include an I-picture, a P-picture and a B-picture, said operation control circuit determines a picture type for a picture based on a picture header included in said video bit stream output from said bit buffer, and, when said underflow of said bit buffer has occurred during decoding of said I-picture or said P-picture, said operation control circuit interrupts said decoding, and continues decoding said video bit stream of said I-picture or P-picture after releasing of said underflow.

19. A video decoding apparatus for decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture and a B-picture to provide decoded pictures, comprising:

a video bit stream analyzer for determining a picture type for each picture included in said video bit stream and analyzing an amount of data of said video bit stream picture by pictures;

a bit buffer for temporarily storing said video bit stream from said video bit stream analyzer;

a decoding circuit for receiving said video bit stream output from said bit buffer and decoding said video bit stream to produce said decoded pictures;

a video bit stream control circuit, operatively connected to said bit buffer and said decoding circuit, for controlling an amount of said video bit stream to be supplied to said decoding circuit from said bit buffer based on an amount of data of said video bit stream stored in said bit buffer;

wherein said control circuit determines whether an amount of data stored in said bit buffer exceeds a threshold value that is predetermined at an amount of said video bit stream which can be safely stored in said bit buffer, said control circuit changes the threshold value in proportion to a playback speed of said decoded pictures;

wherein, when said control circuit determines that the amount of data stored in said bit buffer exceeds the threshold value, said control circuit operates to selectively skip a portion of said video bit stream in each picture in order to prevent said video bit stream from being supplied to said decoding circuit from said bit buffer, and the portion to be skipped is selected based upon the picture type and the amount of data for each picture, detected by said video bit stream analyzer; and

a frame buffer for storing decoded pictures produced by said decoding circuit, said frame buffer comprising;

a forward reference area for storing a decoded I-picture or P-picture to be used in backward prediction decoding to be executed by said decoding circuit;

a backward reference area for storing a decoded I-picture or P-picture to be used in forward prediction decoding to be executed by said decoding circuit; and

a B-picture storage area for storing a decoded B-picture,

wherein said video bit stream control circuit uses said B-picture storage area as an expansion memory for said bit buffer when skipping the B-pictures within said video stream.

20. The video decoding apparatus according to claim 19, wherein said decoding circuit continuously produces two decoded I-pictures or P-pictures in one frame period, stores the first I-picture or P-picture as a reference picture in forward prediction decoding or backward prediction decoding to said B-picture storage area, and outputs the second I-picture or P-picture, which has been decoded later, as a playback picture.

21. A video decoding apparatus for decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture and B-picture to produce decoded pictures, comprising:

a video bit stream analyzer for determining a picture type for each picture included in said video bit stream and analyzing an amount of data of said video bit stream picture by picture;

a bit buffer for temporarily storing said video bit stream from said video bit stream analyzer;

a decoding circuit for receiving said video bit stream output from said bit buffer and decoding said video bit stream to produce said decoded pictures; and

a video bit stream control circuit, operatively connected to said bit buffer and said decoding circuit, for controlling an amount of said video bit stream to be supplied to said decoding circuit from said bit buffer based upon an amount of data of said video bit stream stored in said bit buffer;

wherein said control circuit determines whether an amount of data stored in said bit buffer exceeds a threshold value that is predetermined as an amount of said video bit stream which can be safely stored in said bit buffer, wherein said control circuit changes the threshold value in proportion to a playback speed of said decoded pictures;

wherein, when said control circuit determines that the amount of data stored in said bit buffer exceeds the threshold value, said control circuit operates to selectively skip a portion of said video bit stream in each picture in order to prevent said video bit stream from being supplied to said decoding circuit from said bit buffer, and the portion to be skipped is selected based upon the picture type and the amount of data for each picture detected by said video bit stream analyzer; and

wherein said decoding circuit continuously produces two decoded I-pictures or P-pictures in one frame period, stores the first I-picture or P-picture as a reference picture in forward prediction decoding or backward prediction decoding, and outputs the second I-picture or P-picture, which has been decoded later, as a playback picture.

22. A video decoding apparatus for decoding a coded video bit stream including a series of pictures to produce decoded pictures, wherein said pictures include an I-picture, a P-picture and a B-picture, comprising:

a bit buffer for temporarily storing said video bit stream;

a decoding circuit for receiving said video bit stream output from said bit buffer and decoding said video bit stream to produce said decoded pictures;

an operation control circuit for controlling a reading operation of said bit buffer and a decoding operation of said decoding circuit based on amount of data of said video bit stream stored in said bit buffer, wherein said operation control circuit operates to inhibit said reading operation of said bit buffer and said decoding operation of said decoding circuit in order to supply already decoded pictures during a period from a point of time at which an underflow of said bit buffer has occurred to a point of time at which the underflow is released, and wherein said operation control circuit determines a picture type of said pictures based on a picture header included in said video bit stream output from said bit buffer, and, when said underflow of said bit buffer has occurred during decoding of said I-picture or said P-picture, said operation control circuit interrupts said decoding, and continues decoding said video bit stream of said I-picture or P-picture after releasing of said underflow; and

a frame buffer for storing decoded pictures produced by said decoding circuit, said frame buffer comprising;

a forward reference area for storing a decoded I-picture or P-picture to be used in backward prediction decoding to be executed by said decoding circuit;

a backward reference area for storing a decoded I-picture or P-picture to be used in forward prediction decoding to be executed by said decoding circuit; and

a B-picture storage area for storing a decoded B-picture.

23. The video decoding apparatus according to claim 22,

wherein said operation control circuit controls said frame buffer in such a manner that when a decoded first I-picture or P-picture has been transferred to said forward reference area, a second decoded I-picture or P-picture already stored in said backward reference area or the decoded B-picture stored in said B-picture storage area is read as a playback picture, and that when a decoded third I-picture or P-picture has been transferred to said backward reference area, a fourth decoded I-picture or P-picture already stored in said forward reference area or the decoded B-picture stored in said B-picture storage area is read as said playback picture.