Synchronous read channel employing an expected sample value generator for acquiring a preamble

• US 5,754,352 A
• Filed: 08/22/1996
• Issued: 05/19/1998
• Est. Priority Date: 09/27/1994
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Behrens, Richard T., Dudley, Trent, Bliss, William G.
• Primary Examiner(s): Psitos, Aristotelis M.
• Assistant Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US08/701,572
• Time in Patent Office: 635 Days
• Field of Search: 360/40, 360/51, 375/290, 375/376, 375/322, 375/354, 364/602, 369/48, 369/124, 371/43.8, 330/232, 327/12
• US Class Current: 360/51
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10055 using partial response filtering when writing the signal to the medium or reading it therefrom
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 7/0062 detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

An improved timing recovery phase-locked loop in a partial response recording channel comprising a means for generating a frequency error and a means for generating a phase error represented by a timing gradient. The frequency error is not affected by a DC offset in the input reference signal and is less susciptible to noise due to an increase in sensitivity. A state machine for generating expected samples is used to generate the timing gradient, rather than estimated signal samples, which results in a shorter acquisition preamble. When tracking arbitrary user data, the timing gradient is smoothed to reduce variations in the gain of the loop.

Claims

1. A timing recovery circuit in a synchronous read channel utilized in reading data from a magnetic medium, said synchronous read channel detects digital data from a sequence of discrete time sample values Y(n) generated by sampling pulses in an analog signal from a magnetic read head positioned over the magnetic medium, said timing recovery circuit for adjusting the phase and frequency of a sampling clock signal relative to the phase and frequency of the pulse data, said timing recovery circuit comprises a phase detector circuit comprising:

(a) a timing gradient circuit for generating a timing gradient value .increment.t(n) representing a minimum mean squared error between the discrete time sample values Y(n) and a corresponding a priori sequence of expected sample values X(n) corresponding to sample values of a known acquisition preamble; and

(b) an expected sample value generator for generating the a prior sequence of expected sample values X(n), wherein at least one of the expected sample values X(n) is generated independent from the discrete time sample values.

2. The timing recovery circuit as recited in claim 1, wherein the timing gradient value .increment.t(n) is computed as:

space="preserve" listing-type="equation">.increment.t(n)=Y(n-1)·

X(n)-Y(n)·

X(n-1).

3.

3. The timing recovery circuit as recited in claim 1, wherein the expected sample value generator is initialized to a starting state in response to the sign of two of the discrete time sample values Y(n).

4. The timing recovery circuit as recited in claim 1, wherein the expected sample value generator is initialized to a starting state in response to the sign and absolute magnitude of two of the discrete time sample values Y(n).

5. The timing recovery circuit as recited in claim 1, wherein the expected sample value generator comprises a discrete time counter comprising:

(a) a clock input connected to the sampling clock; and

(b) a discrete time output for outputting the counter value, representing the expected sample value, at the sampling clock rate, wherein the counter is loaded with a starting state value in response to a predetermined number of the discrete time sample values Y(n) and thereafter generates the expected sample values X(n) by sequencing through a plurality of predetermined states at each sample clock period.

6. The timing recovery circuit as recited in claim 1, wherein the timing recovery circuit is utilized in acquiring a known preamble of pulses in a substantially periodic form, wherein:

(a) the expected sample values of the preamble are of the form +A,+A,-A,-A,+A,+A,-A,-A . . . ; and

(b) the +A,+A values of the preamble correspond to a first pair of discrete values on each side, respectively, of the positive pulse peaks; and

(c) the -A,-A values of the preamble correspond to a second pair of discrete values on each side, respectively, of the negative pulse peaks.

7. The timing recovery circuit as recited in claim 1, wherein the timing recovery circuit is utilized in acquiring a known preamble of pulses in a substantially periodic form, wherein:

(a) the expected sample values of the preamble are of the form +A,0,-A,0,+A,0,-A,0. . . ; and

(b) the +A values of the preamble correspond to a first discrete value at the peak of the positive pulses; and

(c) the -A values of the preamble correspond to a second discrete value at the peak of the negative pulses; and

(d) the 0 values of the preamble correspond to a third discrete time value at the beginning and ending of the positive and negative pulses.

8. The timing recovery circuit as recited in claim 1, further comprising:

(a) a circuit for generating a sequence of estimated sample values ˜

X(n) in response to the discrete time sample values Y(n); and

(b) a multiplexer for transmitting to the timing gradient circuit the expected sample values X(n) during acquisition of a predetermined preamble, and the estimated sample values ˜

X(n) during tracking of arbitrary data; and

wherein the timing gradient circuit generates the timing gradient value .increment.t(n) as;

a minimum mean squared error between the discrete time sample values Y(n) and the corresponding sequence of expected sample values X(n) during acquisition; and

a minimum mean squared error between the discrete time sample values Y(n) and the corresponding sequence of estimated sample values ˜

X(n) during tracking.

9. The timing recovery circuit as recited in claim 1, further comprising a variable frequency oscillator having said sampling clock signal as an output, wherein the variable frequency oscillator adjusts the frequency of the sampling clock in response to the timing gradient .increment.t(n).

10. A timing recovery method in a synchronous read channel utilized in reading data from a magnetic medium, said synchronous read channel detects digital data from a sequence of discrete time sample values Y(n) generated by sampling pulses in an analog signal from a magnetic read head positioned over the magnetic medium, said timing recovery method for adjusting the phase and frequency of a sampling clock signal relative to the phase and frequency of the pulse data, said timing recovery method comprising the steps of:

(b) generating an a priori sequence of expected sample values X(n) corresponding to the discrete time sample values of a known acquisition preamble, wherein at least one of the expected sample values X(n) is generated independent from the discrete time sample values; and

(a) generating a timing gradient value .increment.t(n) representing a minimum mean squared error between the discrete time sample values Y(n) and the corresponding a priori sequence of expected sample values X(n).

11. The timing recovery method as recited in claim 10 wherein the timing gradient value .increment.t(n) is computed as:

space="preserve" listing-type="equation">.increment.t(n)=Y(n-1)·

X(n)-Y(n)·

X(n-1).

12.

12. The timing recovery method as recited in claim 10, wherein the expected sample values are generated first in response to the sign of two of the discrete time sample values Y(n).

13. The timing recovery method as recited in claim 10, wherein the expected sample values are generated first in response to the sign and absolute magnitude of two of the discrete time sample values Y(n).

14. The timing recovery method as recited in claim 10, wherein the expected sample values are generated by a discrete time counter comprising:

(a) a clock input connected to the sampling clock; and

(b) a discrete time output for outputting the counter value, representing the expected sample value, at the sampling clock rate, wherein the counter is loaded with a starting state value in response to a predetermined number of the discrete time sample values Y(n) and thereafter generates the expected sample values X(n) by sequencing through a plurality of predetermined states at each sample clock period.

15. The timing recovery method as recited in claim 10, wherein the timing recovery method is utilized in acquiring a known preamble of pulses in a substantially periodic form, wherein:

(a) the expected sample values of the preamble are of the form +A,+A,-A,-A,+A,+A,-A,-A . . . ; and

(b) the +A,+A values of the preamble correspond to a first pair of discrete values on each side, respectively, of the positive pulse peaks; and

(c) the -A,-A values of the preamble correspond to a second pair of discrete values on each side, respectively, of the negative pulse peaks.

16. The timing recovery method as recited in claim 10, wherein the timing recovery circuit is utilized in acquiring a known preamble of pulses in a substantially periodic form, wherein:

(a) the expected sample values of the preamble are of the form +A,0,-A,0,+A,0,-A,0. . . ; and

(b) the +A values of the preamble correspond to a first discrete value at the peak of the positive pulses; and

(c) the -A values of the preamble correspond to a second discrete value at the peak of the negative pulses; and

(d) the 0 values of the preamble correspond to a third discrete time value at the beginning and ending of the positive and negative pulses.

17. The timing recovery method as recited in claim 10, further comprising the steps of:

(a) generating a sequence of estimated sample values ˜

X(n) in response to the discrete time sample values Y(n); and

(b) transmitting to the timing gradient circuit the expected sample values X(n) during acquisition of a predetermined preamble, and the estimated sample values ˜

X(n) during tracking of arbitrary data; and

wherein the timing gradient value .increment.t(n) represents;

a minimum mean squared error between the discrete time sample values Y(n) and the corresponding sequence of expected sample values X(n) during acquisition; and

a minimum mean squared error between the discrete time sample values Y(n) and the corresponding sequence of estimated sample values ˜

X(n) during tracking.

18. The timing recovery method as recited in claim 10, further comprising the steps of:

(c) generating the sampling clock signal as the output of a variable frequency oscillator; and

(d) adjusting the output of the variable frequency oscillator in response to the timing gradient .increment.t(n).