Adaptive power management processes, circuits and systems

• US 5,754,436 A
• Filed: 11/06/1996
• Issued: 05/19/1998
• Est. Priority Date: 12/22/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Brown, Jacqueline, Walsh, James J.
• Primary Examiner(s): Trammell, James P.
• Application Number:
  US08/744,567
• Time in Patent Office: 559 Days
• Field of Search: 364/483, 364/707, 307/66, 377/16, 395/838, 395/839, 395/878, 395/889, 395/750, 395/835, 395/845, 395/882
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 11/3423 where the assessed time is active or idle time
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions

Abstract

A system (100) for computer power management for a computer (102) having a clock (706), includes a plurality of sampling circuits (2360, 2350, 4630, 4720, 4810, 3400, 5300, 5400) responsive to different system activity levels and producing system activity signals representative of the system activity levels. More circuitry (120, 106, 4640) is responsive to the system activity signals and supplies weighted activity output signals adjustably weighting the system activity levels. Filter circuitry (702, 4680) continually responds to the weighted activity output signals to produce a series of duty cycle-related control signals (TONTOFF) representative of directions to pulse-width modulate (MASKCLK) the clock of the computer with such duty cycle. Other devices, systems and methods are also disclosed.

Claims

1. A system for computer power management for a computer having a clock, comprising:

a plurality of sampling circuits responsive to different system activity levels and producing system activity signals representative of the system activity levels;

circuitry responsive to the system activity signals and supplying weighted activity output signals adjustably weighting the system activity levels; and

filter circuitry continually responsive to the weighted activity output signals to produce a series of duty-cycle-related control signals representative of directions to pulse-width modulate the clock of the computer with such duty cycle.

2. The system of claim 1 wherein said filter circuitry is further responsive to the system activity levels and the duty-cycle-related control signals to supply weight-adjustment signals to said circuitry supplying weighted output signals.

3. A computer system having peripherals, comprising:

a peripheral processing unit (PPU) having a plurality of peripheral event counting circuits responsive to different system activity levels and producing system activity signals representative of the system activity levels, said PPU further having a variable pulse width generator supplying pulses with a duty cycle established by duty cycle control data input thereto; and

a microprocessor unit (MPU) having a clock circuit, and further circuitry responsive to the system activity signals and supplying weighted activity output signals adjustably weighting the system activity levels and filteringly responsive to the weighted activity output signals to supply a series of the duty cycle control data representative of directions to pulse-width modulate the clock circuit with such duty cycle, said clock circuit having an input connected to receive the pulses from said variable pulse width generator in said PPU.

4. A process for power management of a computer system having a clock, comprising the steps of:

sampling different system activity levels and producing system activity signals representative of the system activity levels;

supplying weighted activity output signals adjustably weighting the system activity levels; and

continually filtering the weighted activity output signals to produce a series of duty-cycle-related control signals representative of directions to pulse-width modulate the clock of the computer with such duty cycle.

5. The process of claim 4 wherein said filtering step includes:

computing a criterion function value as a function of the system activity levels; and

updating the duty-cycle-related control signal based on the criterion function value.

6. The process of claim 4 wherein said filtering step includes:

computing successive criterion function values as a function of the system activity levels over time; and

updating the duty-cycle-related control signal based on an average of criterion function values.

7. The process of claim 4 wherein said filtering step includes:

computing a criterion function value as a function of the system activity levels;

updating the duty-cycle-related control signal based on the criterion function value when that value lies in a predetermined range; and

halting the system when the criterion function value lies outside the range in one direction and running the system with 100% duty cycle clock when the criterion function value lies outside the range in the other direction.

8. A personal computer comprising:

provision for user input;

a memory;

provision for user output;

a microprocessor coupled to said provision for user input, said memory, and said provision for user output;

a plurality of sampling circuits responsive to different system activity levels and producing system activity signals representative of said system activity levels;

circuitry responsive to said system activity signals and supplying weighted activity output signals adjustably weighting said system activity levels; and

filter circuitry responsive to said weighted activity output signals to produce a series of duty-cycle-related control signals representative of directions to pulse-width modulate a clock of said computer.

9. The personal computer of claim 8 wherein said filter circuitry is further responsive to said system activity levels and said duty-cycle-related control signals to supply weight-adjustment signals to said circuitry supplying weighted output signals.

10. The personal computer of claim 8 further comprising an input device connected to said input connector.

11. The personal computer of claim 8 wherein said provision for output comprises an output connector.

12. The personal computer of claim 8 further comprising a display connected to said output connector.

13. A personal computer comprising:

an input device;

a memory;

a display;

a peripheral processing unit (PPU) having a plurality of peripheral event counting circuits responsive to different system activity levels and producing system activity signals representative of said system activity levels, said PPU further having a variable pulse width generator supplying pulses with a duty cycle established by duty cycle control data input thereto; and

a microprocessor unit (MPU) coupled to said input device, said memory, and said display, said MPU having circuitry responsive to said system activity signals, said circuitry supplying weighted activity output signals by adjustably weighting said system activity levels and said circuitry supplying, by filtering in response to said weighted activity output signals, a series of said duty cycle control data to said variable pulse width generator, said MPU further comprising a clock circuit having an input connected to receive said pulses from said variable pulse width generator in said PPU.

14. The personal computer of claim 13 wherein said circuitry comprises weighting circuitry for supplying said weighted activity output signals and filtering circuitry for supplying said series of duty cycle control data.

15. The personal computer of claim 14 wherein said filtering circuitry is further responsive to said system activity levels and said duty cycle control data to supply weight-adjustment signals to said weighting circuitry.

16. The personal computer of claim 13 wherein said input device includes a keyboard.

17. The personal computer of claim 13 wherein said display includes a CRT.

18. The personal computer of claim 13 wherein the personal computer has the form of a notebook computer.

19. An electronic wiring board article of manufacture comprising:

a printed wiring board having a substantially insulative planar board element, conductors in or on said board element; and

a first integrated circuit mounted on said printed wiring board said first integrated circuit comprising;

a peripheral processing unit (PPU) having a plurality of peripheral event counting circuits responsive to different system activity levels and producing system activity signals representative of the system activity levels, said PPU further having a variable pulse width generator supplying pulses with a duty cycle established by duty cycle control data input thereto;

a second integrated circuit mounted on said printed wiring board said second integrated circuit comprising;

a microprocessor unit (MPU) coupled to said input device, said memory, and said display, said MPU having circuitry responsive to said system activity signals, said circuitry supplying weighted activity output signals by adjustably weighting said system activity levels and supplying, by filtering in response to said weighted activity output signals, a series of said duty cycle control data to said variable pulse width generator, said MPU further comprising a clock circuit having an input connected to receive said pulses from said variable pulse width generator in said PPU; and

said conductors of said printed wiring board comprising one or more conductors connecting said first integrated circuit to said second integrated circuit.

20. The electronic wiring board of claim 19 wherein said circuitry further comprises weighting circuitry for supplying said weighted activity output signals and filtering circuitry for supplying said series of duty cycle control data.

21. The electronic wiring board of claim 20 wherein said filtering circuitry is further responsive to said system activity levels and said duty cycle control data to supply weight-adjustment signals to said weighting circuitry.