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Negative charge pump circuit for electrically erasable semiconductor memory devices

  • US 5,754,476 A
  • Filed: 10/31/1996
  • Issued: 05/19/1998
  • Est. Priority Date: 10/31/1995
  • Status: Expired due to Term
First Claim
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1. A negative charge pump circuit, comprising:

  • a plurality of charge pump stages, each charge pump stage having an input node and an output node and comprising a pass transistor and a first coupling capacitor, the pass transistor having a first terminal connected to the input node, a second terminal connected to the output node and a control terminal connected to an internal node of the charge pump stage, said first coupling capacitor having a first plate connected to said output node and a second plate connected to a respective clock signal; and

    negative voltage regulation means for regulating a negative output voltage on an output node of the negative charge pump circuit to provide a fixed negative voltage value, comprising at least one negative voltage limiting means electrically coupling said output node of the negative charge pump circuit with the internal node of the last charge pump stage of the negative charge pump circuit to limit the negative voltage on said internal node and on the output node of said last charge pump stage.

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