Negative charge pump circuit for electrically erasable semiconductor memory devices
First Claim
1. A negative charge pump circuit, comprising:
- a plurality of charge pump stages, each charge pump stage having an input node and an output node and comprising a pass transistor and a first coupling capacitor, the pass transistor having a first terminal connected to the input node, a second terminal connected to the output node and a control terminal connected to an internal node of the charge pump stage, said first coupling capacitor having a first plate connected to said output node and a second plate connected to a respective clock signal; and
negative voltage regulation means for regulating a negative output voltage on an output node of the negative charge pump circuit to provide a fixed negative voltage value, comprising at least one negative voltage limiting means electrically coupling said output node of the negative charge pump circuit with the internal node of the last charge pump stage of the negative charge pump circuit to limit the negative voltage on said internal node and on the output node of said last charge pump stage.
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Abstract
A negative charge pump circuit having a plurality of charge pump stages. Each charge pump stage has an input node and an output node and includes a pass transistor and a first coupling capacitor. The pass transistor has a first terminal connected to the input node, a second terminal connected to the output node and a control terminal connected to an internal node of the charge pump stage. The first coupling capacitor has a first plate connected to said output node and a second plate connected to a respective clock signal. Negative voltage regulation means are provided for regulating a negative output voltage on an output node of the negative charge pump circuit to provide a fixed negative voltage value. The negative charge pump circuit includes at least one negative voltage limiting means electrically coupling said output node of the negative charge pump circuit with the internal node of the last charge pump stage of the negative charge pump circuit. The negative voltage limiting means limits the negative voltage on the internal node and on the output node of said last charge pump stage.
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Citations
22 Claims
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1. A negative charge pump circuit, comprising:
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a plurality of charge pump stages, each charge pump stage having an input node and an output node and comprising a pass transistor and a first coupling capacitor, the pass transistor having a first terminal connected to the input node, a second terminal connected to the output node and a control terminal connected to an internal node of the charge pump stage, said first coupling capacitor having a first plate connected to said output node and a second plate connected to a respective clock signal; and negative voltage regulation means for regulating a negative output voltage on an output node of the negative charge pump circuit to provide a fixed negative voltage value, comprising at least one negative voltage limiting means electrically coupling said output node of the negative charge pump circuit with the internal node of the last charge pump stage of the negative charge pump circuit to limit the negative voltage on said internal node and on the output node of said last charge pump stage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for producing a negative charge voltage for erasure of a memory cell using a plurality of charge pump stages, comprising the steps of:
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a) enabling a reference potential for said plurality of charge pump stages; b) supplying first and second signals at first time intervals to a first stage of said plurality of charge pump stages and establishing a first negative charge voltage value at a first input node; c) supplying said first and second signals at second time intervals to said first stage for driving said first negative voltage to a second input node; d) supplying third and fourth signals at third time intervals to a second stage of said plurality of charge pump stages and establishing a second negative charge voltage value at said second input node, said first and second negative voltages establish a cumulative voltage greater than said first or second negative voltages; e) supplying said third and fourth signals at fourth time intervals to said second stage for driving said cumulative negative voltage to a third input node; f) limiting said cumulative negative voltage; g) regulating said limited cumulative negative voltage; and h) erasing said memory cell using said regulated cumulative negative voltage. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A negative charge pump circuit for erasure of a memory cell comprising:
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an enablement transistor coupled to a reference potential; a first stage having input and output nodes and a first threshold voltage cancellation circuit, said input node being coupled to said enablement transistor and said first stage providing a first negative charge pump voltage at said first output node compensated by said first cancellation circuit; a first pair of clock signals respectively coupled to an intermediate node and said output node of said first stage for driving said first negative charge pump voltage; a second stage having input and output nodes and a second threshold voltage cancellation circuit, said second input node being coupled to said first output node and said second stage providing a second negative charge pump voltage at said second output node, said second voltage being equal to approximately twice the negative voltage value as said first voltage and includes said first voltage; a second pair of clock signals coupled to an intermediate node and said output node of said second stage for driving said second negative charge pump voltage; and a voltage regulation circuit being coupled between said second stage output and an erasure voltage output terminal. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification