Semiconductor memory tester with hardware accelerators
First Claim
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1. A semiconductor memory manufacturing system of the type which manufactures semiconductor memories having rows and columns of memory cells and redundant rows and columns that can be substituted for rows and columns in the semiconductor memory to replace faulty memory cells, comprising:
- a) a test sub-system adapted to determine whether each of the cells in a memory under test is faulty, the test system having a catch memory storing failure indications for the cells in the memory under test;
b) an analysis sub-system adapted to determine which rows and columns of the memory under test should be replaced by redundant rows or columns, the analysis sub-system including an analysis memory; and
c) data transfer circuitry connecting the catch memory to the analysis memory, the data transfer circuitry comprising;
i) electronic circuitry for determining, based on the information stored in the catch memory, when a row or column in said semiconductor memory must be replaced and then inhibiting transfer of indications of faulty cells in that row or column; and
ii) data encoding circuitry, connected to the electronic circuitry, for passing to the analysis memory indications of the faulty cells not inhibited by the electronic circuitry.
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Abstract
A semiconductor memory manufacturing system including a tester sub-system and a redundancy analysis sub-system. The manufacturing system includes a transfer circuit between the test sub-system and the redundancy analysis sub-system that reduces the number of bits of data transferred to the redundancy analyzer. This speeds up the transfer process and also speeds up the redundancy analysis.
73 Citations
20 Claims
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1. A semiconductor memory manufacturing system of the type which manufactures semiconductor memories having rows and columns of memory cells and redundant rows and columns that can be substituted for rows and columns in the semiconductor memory to replace faulty memory cells, comprising:
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a) a test sub-system adapted to determine whether each of the cells in a memory under test is faulty, the test system having a catch memory storing failure indications for the cells in the memory under test; b) an analysis sub-system adapted to determine which rows and columns of the memory under test should be replaced by redundant rows or columns, the analysis sub-system including an analysis memory; and c) data transfer circuitry connecting the catch memory to the analysis memory, the data transfer circuitry comprising; i) electronic circuitry for determining, based on the information stored in the catch memory, when a row or column in said semiconductor memory must be replaced and then inhibiting transfer of indications of faulty cells in that row or column; and ii) data encoding circuitry, connected to the electronic circuitry, for passing to the analysis memory indications of the faulty cells not inhibited by the electronic circuitry. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor memory manufacturing system of the type which manufactures semiconductor memories having rows and columns of memory cells and redundant rows and columns that can be substituted for rows and columns in the semiconductor memory to replace faulty memory cells, comprising:
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a) a test sub-system adapted to determine whether each of the cells in a memory under test is faulty, the test system having a catch memory storing failure indications for the cells in the memory under test; b) an analysis sub-system adapted to determine which rows and columns of the memory under test should be replaced by redundant rows or columns, the analysis sub-system including an analysis memory; and c) data transfer circuitry connecting the catch memory to the analysis memory, the data transfer circuitry comprising means for encoding a stream of data values indicating faults in a memory under test, the means for encoding providing an output value having a plurality of fields with at least a first of the plurality of fields indicating the address of a faulty cell in the memory under test and at least a second of the plurality of fields indicating whether there is a fault in the cell at an address having a predetermined relationship to the address in the first of the plurality of fields. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. A semiconductor memory manufacturing system of the type which manufactures semiconductor memories having rows and columns of memory cells and redundant rows and columns that can be substituted for rows and columns in the semiconductor memory to replace faulty memory cells, comprising:
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a) a test sub-system adapted to determine whether each of the cells in a memory under test is faulty, the test subsystem generating a stream of data values, each data value indicating whether a cell in a memory under test is faulty; b) an analysis sub-system, receiving an input data stream having values indicating the locations of faults within a memory under test, to determine which rows and columns of the memory under test should be replaced by redundant rows or columns; c) data transfer circuitry having an input receiving the stream of data values from the test sub-system and an output providing a data stream to the input of the analysis sub-system, the data transfer circuitry including electronic circuitry for determining, based on the information at its input, when a row or column in said semiconductor memory under test must be replaced and then inhibiting transfer of indications of faulty cells in that row or column. - View Dependent Claims (18, 19, 20)
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Specification