Byte-parallel system for implementing reed-solomon error-correcting codes

• US 5,754,563 A
• Filed: 09/11/1995
• Issued: 05/19/1998
• Est. Priority Date: 09/11/1995
• Status: Expired due to Term

• Current Assignee: ECC Technologies Inc.
• Original Assignee: ECC Technologies Inc.
• Inventors: White, Philip E.
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US08/526,088
• Time in Patent Office: 981 Days
• Field of Search: 371/376, 371/40.17, 371/37.11, 364/746.1, 364/754
• US Class Current: 714/757
• CPC Class Codes: H03M 13/151 using error location or error correction polynomials

Abstract

A high-speed byte-parallel pipelined error-correcting system for Reed-Solomon codes includes a parallelized and pipelined encoder and decoder and a feedback failure location system. Encoding is accomplished in a parallel fashion by multiplying message words by a generator matrix. Decoding is accomplished with or without byte failure location information by multiplying the received word by an error detection matrix, solving the key equation and generating the most-likely error word and code word in a parallel and pipelined fashion. Parallelizing and pipelining allows inputs to be received at very high (fiber optic) rates and outputs to be delivered at correspondingly high rates with minimum delay. The error-correcting system can be used with any type of parallel data storage or transmission media to create an arbitrary level of fault-tolerance and allows previously considered unreliable media to be effectively used in highly reliable memory or communications systems.

Claims

1. A parallel encoder for generating R redundant bytes responsive to receiving a message word having K variable message bytes for forming a code word having N=K+R bytes, wherein each of the bytes is an element of a finite field and includes w binary bits, and K and R are positive integers;

said parallel encoder including;

R redundant byte generators, each receiving a message word in byte-parallel fashion and moving each of the variable message bytes through a multiplying stage, thereby to generate K intermediate product bytes, each of the intermediate product bytes representing one of said variable message bytes multiplied by a different one of K constant generator bytes, wherein each of the constant generator bytes is a predetermined constant element of the finite field; and

wherein each redundant byte generator further includes byte adder circuitry for receiving the intermediate product bytes in parallel and for pairing said intermediate product bytes for addition in a plurality of successive byte-additive stages including a final byte-additive stage that generates its associated one of R redundant bytes.

2. The parallel encoder of claim 1 wherein:

each of said redundant byte generators includes K byte multiplier circuits, each said byte multiplier circuit receiving a different one of said K variable message bytes and generating an associated one of said K intermediate product bytes.

3. The parallel encoder of claim 2 wherein:

each one of said byte multiplier circuits includes w product bit generator circuits in parallel, each said product bit generator circuit including w bit multiplier circuits, each bit multiplier circuit receiving a different one of w variable bits forming the associated variable message byte and generating an intermediate product bit representing the product of its associated one of the variable message bits and an associated one of w constant bits determined by the associated generator byte where each constant bit is predetermined to equal either 0 or 1; and

bit adder circuitry associated with the bit multiplier circuits for receiving the intermediate product bits in parallel and for pairing the intermediate product bits for addition in successive bit-additive stages including a final bit-additive stage for generating its associated one of w bits that together form the intermediate byte associated with said one byte multiplier circuit.

4. The parallel encoder of claim 3 wherein:

said bit adder circuitry includes a plurality of exclusive OR (XOR) logic gates arranged in n said stages, where n is an integer satisfying the relationship 2ⁿ ≧

w, with each XOR gate in a first one of the bit-additive stages receiving two of the intermediate product bits and providing a single bit output to an XOR gate of a subsequent stage.

5. The parallel encoder of claim 1 wherein:

said byte adder circuitry includes a plurality of byte adders arranged in m byte-additive stages where m is the lowest integer satisfying the relationship 2^m ≧

K, with each of the byte adders in a first of said byte-additive stages receiving two of said intermediate product bytes and providing a single byte output to a byte adder of a subsequent stage.

6. The parallel encoder of claim 5 wherein:

each of said byte adders includes w exclusive OR (XOR) logic gates in parallel.

7. The parallel encoder of claim 1, wherein:

said redundant byte generators are fabricated on a single semiconductor chip.

8. In a system for parallel encoding of message words into code words provided to data channels, and for parallel decoding of an output of the data channels comprised of received words, each received word having a plurality of variable received word bytes and each variable received word byte including w binary bits where w is an integer greater than one, circuitry for generating a syndrome word in response to inputting a received word of K variable message bytes and R variable redundant bytes, where K and R are positive integers;

said circuitry including;

R syndrome byte generators, each syndrome byte generator having as a parallel input a received word, and moving the received word through a multiplying stage to generate N intermediate product bytes where N=K+R, each intermediate product byte representing a multiplication of one of N variable received bytes of the received word by an associated one of N predetermined constant error detection bytes; and

wherein each syndrome byte generator further includes byte adder circuitry for receiving the intermediate product bytes in parallel and for pairing of the intermediate product bytes for addition in successive byte-additive stages including a final byte-additive stage for generating its associated one of R syndrome bytes.

9. The syndrome generating circuitry of claim 8 wherein:

each of the syndrome byte generators includes N byte multiplier circuits, each of the byte multiplier circuits receiving a different one of the variable received word bytes and generating an associated one of the intermediate product bytes.

10. The syndrome generating circuitry of claim 9, wherein:

each one of said byte multiplier circuits includes w product bit generator circuits arranged in parallel, each said product bit generator circuit including w bit multiplier circuits, each bit multiplier circuit receiving a different one of the w variable input bits of the associated variable received word byte and generating an intermediate product bit representing the product of its associated variable input bit and an associated one of w predetermined constant bits of said constant error detection byte; and

bit adder circuitry associated with the bit multiplier circuits for receiving the intermediate product bits in parallel and for pairing them for addition in successive bit-additive stages including a final bit-additive stage for generating its associated one of w intermediate product bits that together form the intermediate product byte associated with said one byte multiplier circuit.

11. The syndrome generating circuitry of claim 8 wherein:

said byte adder circuitry includes a plurality of byte adders arranged in m byte-additive stages where m is an integer satisfying the relationship 2^m ≧

N, each of the adders in a first one of said byte-additive stages receiving a pair of the intermediate product bytes and providing a single byte output to a subsequent stage.

12. The syndrome generating circuitry of claim 11 wherein:

each of said byte adders includes w exclusive OR (XOR) logic gates in parallel.

13. In a system for parallel encoding and decoding of data in which the data take the form of message words having K message bytes and code words having N=K+R bytes where R is the number of redundant bytes, wherein the code words are provided to a plurality of data channels in parallel and a parallel output of the data channels takes the form of received words, a decoding system including:

a syndrome generator for generating a syndrome polynomial responsive to receiving a received word as an input;

a key equation solver circuit for generating an error locator polynomial L(x) and an error evaluator polynomial V(x) representative of solutions to the key equation;

space="preserve" listing-type="equation">S(x)L(x)=V(x) modulo x.sup.R+1

where R is the number of redundant bytes and S(x) is said syndrome polynomial; and

a most-likely error word generating circuit for generating a most-likely error word based on receiving said error locator polynomial and said error evaluator polynomial.

14. The system of claim 13, wherein:

said key equation solving circuit includes R successive stages, each stage generating an output representing a single iteration of an iterative algorithm for solving said key equation.

15. The system of claim 13 wherein:

said most likely error word generating circuit includes N most-likely error byte generating circuits, each one of the error byte generating circuits receiving the error locator polynomial and the error evaluator polynomial in parallel and, based on the error locator polynomial, the error evaluator polynomial and a first derivative of the error locator polynomial, generating a most-likely error byte, the most likely error bytes of the respective most-likely error byte generating circuits together providing the most-likely error word.

16. The system of claim 15 wherein:

each of the error byte generating circuits includes a first evaluator circuit receiving the error locator polynomial for generating an error locator byte, a second evaluator circuit receiving the first derivative of the error locator polynomial and generating a derivative byte, and a third evaluator circuit receiving the error evaluator polynomial and generating an evaluator byte;

a test circuit receiving the error locator byte as an input, and generating an output that varies depending upon whether or not the error locator byte is equal to zero;

a byte multiplier receiving as its input said error evaluator byte and a reciprocal of said derivative byte and generating an output representative of the error evaluator byte divided by the first derivative byte; and

w AND logic gates, each of said gates receiving (i) the output of said test circuit; and

(ii) a different one of the output bits of said multiplier, and generating as its output an error bit whereby said logic gates together output a most-likely error byte.

17. The system of claim 13, further including:

a most-likely code word generator for receiving as inputs said received word and said most-likely error word, and generating as its output a most-likely code word.

18. The system of claim 17 wherein:

said most-likely code word generator includes N byte adder circuits, each byte adder circuit receiving one of N received word bytes of said received word and further receiving one of N most-likely error word bytes of said most-likely error word, and providing as an output a most-likely code word byte representing the sum (XOR) of the associated most-likely error word byte and received word byte.

19. The system of claim 18 wherein:

each of said byte adder circuits includes w exclusive OR logic gates in parallel.

20. The system of claim 18 further including:

a multiplexing circuit receiving as inputs said most-likely error word, said most-likely code word and said received word, and a select control means for causing the multiplexing circuit to provide one of said inputs as its output.

21. An error correcting system including:

a parallel encoder for receiving message words, each message word including K message bytes where each of the message bytes includes w binary bits, said parallel encoder generating as its output a code word having N bytes including the message bytes plus R redundant bytes;

N parallel data channels for receiving the code word in byte parallel fashion and providing a parallel data channel output based on the code word;

a parallel decoder for receiving the parallel data channel output as a received word and, based on the received word, generating a most-likely error word and a most-likely code word each having N bytes; and

a failure location system, coupled to receive failure location information from said data channels and further coupled to provide byte failure location information to the parallel decoder, said failure location system including a microprocessing means for sequentially reading every location in the data handling channels and accumulating failure information associated with each of said locations;

said processor system being adapted to identify at least one of said locations as a failed location based on a sensed frequency of errors at least equal to a predetermined threshold frequency;

said failure location system further including a memory means for storing a record of failed locations, said memory providing the byte failure location information to the parallel decoder.

22. The error correcting system of claim 21 wherein:

said memory means includes a content addressable memory, a random access memory, and an address selector coupled between the content addressable memory and the random access memory for providing an address to said random access memory, said random access memory fetching information at said address to provide the byte failure location information.

23. The error correcting system of claim 22 wherein:

said content addressable memory includes an address counter, multiple beginning-address-of-failure registers for storing the beginning address of failed locations, and multiple comparators, each comparator receiving the output of said address counter and an associated one of the beginning-address-of-failure registers;

each comparator, upon determining a match between the address counter output and the output of its associated beginning-address-of-failure register, causing an address encoder to generate an output, corresponding to the identified address based on the selective comparator, to an address register of said random access memory.

24. A variable byte multiplier circuit for multiplying two variable data bytes wherein each of the variable data bytes is composed of w data bits and w is an integer greater than one;

said variable-byte multiplier circuit including;

w constant byte multipliers in parallel, each one of the constant byte multipliers receiving a first variable byte in parallel and generating a first intermediate byte representing the product of the first variable byte and a constant byte corresponding to said one constant byte multiplier, wherein each of the constant bytes is a predetermined constant element of a finite field;

w logic sets in parallel for receiving a second variable byte, each of said logic sets receiving a different one of w bits of the second variable byte and further receiving a different one of said first intermediate bytes;

wherein each one of said logic sets includes w AND logic gates in parallel, each of the AND logic gates receiving as bit inputs (i) the bit of said second variable byte corresponding to said one logic set, and (ii) a different one of w bits of the first intermediate byte that corresponds to said one logic set;

each of said logic gates performing an AND logic function on its inputs to generate an intermediate bit, with the logic gates of the logic set together generating a second intermediate byte composed of the intermediate bits; and

byte adder circuitry for receiving the second intermediate bytes from said logic sets in parallel and for pairing said second intermediate bytes in a plurality of successive byte-additive stages including a final byte-additive stage that generates a resultant byte representing a product of the first and second variable bytes.

25. The variable byte multiplier circuit of claim 24 wherein:

said byte adder circuitry includes a plurality of byte adders arranged in m said byte-additive stages, where m is the lowest integer satisfying the relationship 2^m ≧

w, with each of the byte adders in a first one of the byte-additive stages receiving two of the second intermediate bytes and providing a single byte output to a byte adder of a subsequent byte-additive stage.

26. The variable byte multiplier circuit of claim 25 wherein:

each of said byte adders includes w exclusive OR (XOR) logic gates in parallel;

wherein the XOR gates of the final byte additive stage generate, as respective single bit outputs, the w bits of the resultant byte.

27. The variable byte multiplier circuit of claim 24 wherein:

each of said w constant byte multipliers includes w product bit generators, with each said product bit generator including w constant bit multiplier circuits for receiving a variable input byte in parallel, with each of the constant bit multiplier circuits receiving a different one of w variable input bits of the first variable byte and, responsive thereto, generating one of w intermediate product bits representing a product of the associated one of said w variable input bits and a predetermined constant bit, said bit multiplier circuits together generating w intermediate product bits; and

bit adder circuitry associated with each constant bit multiplier for receiving the intermediate product bits in parallel, and for pairing the intermediate product bits for addition in successive bit-additive stages including a final stage for generating a single bit output associated with said product bit generator circuit; and

wherein the single bit outputs of all of said final stages together provide said first intermediate byte.

28. In a system for parallel decoding of an output of parallel data channels in the form of received words having N=K+R bytes where K is the number of data bytes and R is the number of redundant bytes, a key equation solving circuit for receiving a syndrome product of a constant polynomial x and a syndrome polynomial S(x) of R bytes based on the received words from the parallel data channels, and generating an error locator polynomial L(x) and an error evaluator polynomial V(x) representing a solution to the key equation:

space="preserve" listing-type="equation">S(x)L(x)=V(x) modulo x.sup.R+1

said key equation solving circuit including;

R successive stages, each stage receiving a byte-parallel input and generating a byte-parallel output representing a single iteration of an iterative algorithm for solving the key equation, wherein a first one of said stages receives said syndrome product, and wherein the stage output of a final one of said stages includes said error locator polynomial L(x) and an evaluator product of said error evaluator polynomial V(x) and said polynomial x.

29. The key equation solving circuit of claim 28 further including:

a polynomial multiplier for receiving the syndrome polynomial, and generating a multiplier output representing the syndrome product and providing the multiplier output to said initial stage.

30. The key equation solving circuit of claim 29 further including:

a means for providing predetermined byte failure location information to said initial stage, whereby said stage output of the final stage is based in part on said byte failure location information.

31. The key equation solving circuit of claim 30 wherein:

each of said stages includes polynomial processing circuitry having first and second alternative settings for performing corresponding first and second different operations upon the stage input to said stage; and

control circuitry in parallel with the polynomial processing circuitry and operatively coupled to the polynomial processing circuitry for selecting one of said alternative settings to cause the polynomial processing circuitry to perform the operation corresponding to the selected setting on said stage input to said stage.

32. The key equation solving circuit of claim 30 wherein:

each of said stages comprises an incrementing circuit and two polynomial multiplying circuits, each of which multiplies an incoming polynomial by said constant polynomial x;

a control circuit for determining whether incoming data satisfies a certain condition, an integer subtracter circuit, a byte selector, two polynomial selectors, and a plurality of polynomial multipliers; and

an integer selector, and a plurality of polynomial adder circuits for generating respective outputs, each representing the sum of two incoming data polynomials.

33. In a system for parallel decoding of data channel output of received words having N=K+R bytes where K is the number of data bytes and R is the number of redundant bytes, including a key equation solving circuit for receiving the product of a constant polynomial x and a syndrome polynomial S(x) of R bytes and generating an error locator polynomial L(x) and error evaluator polynomial V(x) representing a solution to the key equation:

space="preserve" listing-type="equation">S(x)L(x)=V(x) modulo x.sup.R+1 ;

a most-likely error word generator, including;

N most-likely error byte generating circuits, each one of the error byte generating circuits receiving the error locator polynomial an d the error evaluator polynomial in parallel and, based on the error locator polynomial, the error evaluator polynomial and a first derivative of the error locator polynomial, generating a most-likely error byte, the most-likely error bytes of the respective most-likely err or byte generating circuits together providing the most-likely error word.

34. The most-likely error word generator of claim 33 wherein:

each of the error byte generating circuits includes a first evaluator circuit receiving the error locator polynomial for generating an error locator byte, a second evaluator circuit receiving the first derivative of the error locator polynomial and generating a derivative byte, and a third evaluator circuit receiving the error evaluator polynomial and generating an evaluator byte;

a test circuit receiving the error locator byte as an input, and generating an output that varies depending upon whether or not the error locator byte is equal to zero;

a byte multiplier receiving as its inputs said error evaluator byte and a reciprocal of said derivative byte and generating an output representative of the error evaluator byte divided by the first derivative byte; and

w AND logic gates, each of said gates receiving (i) the output of said test circuit, and (ii) a different one of the output bits of said multiplier, and generating as its output an error bit whereby said logic gates together output a most-likely error byte.

35. In combination with the most-likely error word generator of claim 34:

a most-likely code word generator for receiving as inputs said received word and said most-likely error word, and generating as its output a most-likely code word.

36. The combination of claim 35 wherein:

said most-likely code word generator includes N byte adder circuits, each byte adder circuit receiving one of N received word bytes of said received word and further receiving one of N most-likely error word bytes of said most-likely error word, and providing as an output a most-likely code word byte representing the sum of the associated most-likely error word byte and code word byte.

37. The combination of claim 36 wherein:

each of said byte adder circuits includes w exclusive OR logic gates in parallel.

38. The combination of claim 37 further including:

a multiplexing circuit receiving as inputs said most-likely error word, said most-likely code word and said received word, and a select control means for causing the multiplexing circuit to provide a selected one of said inputs as its output.