Combination of input output circuitry and local area network systems

• US 5,754,764 A
• Filed: 02/22/1994
• Issued: 05/19/1998
• Est. Priority Date: 02/22/1994
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Davis, Timothy D., Masood, Ahmed, Fung, Hon C., Baker, Roman, Waterson, Kent Bruce, Michael, Martin S., Koether, Mark Douglas, Johnson, J. Scott, Daugherty, Dan E.
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): DAVIS JR, WALTER D
• Application Number:
  US08/200,097
• Time in Patent Office: 1,547 Days
• Field of Search: 395/800, 395/200, 395/250, 395/275, 364/DIG. 1, 375/62
• US Class Current: 709/200
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 12/28 characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks] wireless communication networks H04W ; arrangements for dividing the transmission path H04W40/00
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

Input/output and local area network functions are combined into a single integrated circuit on a single semiconductor (e.g., a single piece of silicon). Preferred system embodiments on a single integrated circuit are typically placed inside a host system (e.g., a personal computer based on Intel®'"'"'s 286, 386, 486, and Pentium microprocessors) and interrelate with standard operating systems (e.g., Microsoft®'"'"'s DOS, IBM®'"'"'s OS/2) on traditional, commonly used bus architectures (e.g., Industry Standard Architecture and Enhanced Industry Standard). Local area network circuitry and input and output circuitry are both coupled to at least one host system (and indirectly to potentially any number of host systems tied together via the local area network system) via a common data bus. The input and output circuitry couples the host system to at least one input/output channels. Examples of the types of input/output channels are a first serial interface, a second serial interface, a parallel port, a hard drive, a floppy drive, and/or any combination thereof.

Claims

1. An integrated circuit, comprising

(a) at least one data bus to electrically couple said integrated circuit with a first host system, sad at least one data bus transfers data packaged in at least one data packet to and from said integrated circuit;

(b) local area network circuitry electrically coupled to said at least one data bus and selectively to a network, said local area network circuitry to electrically couple said integrated circuit and, in turn, said first host system to said network and thereby to at least one second host system via said at least one data bus, said network transfers data packaged in said at least one data packet to and from said local area network circuitry;

(c) input and output circuitry electrically coupled to said at least one data bus, said input and output circuitry to electrically couple said integrated circuit and, in turn, said first host system to at least one input/output channel, said input/output channel selectively electrically coupled to at least one external electrical module, said at least one input/output channel transfers said data packaged in said at least one data packet to and from said input and output circuitry wherein said at least one input/output channel is selected from a group consisting of a first serial port interface, a second serial port interface, a parallel port interface, a hard drive, a floppy drive, and any combination thereof,

(d) first memory electrically coupled to said local area network circuitry and to said input and output circuitry and to said at least one data bus, said first memory to store data received and transmitted by said local area network circuitry and sad input and output circuitry via said at least one data bus and said network and said at least one input/output channel, said first memory is configurable and has sufficient memory capacity to store more than one data packet of said at least one data packet; and

(e) a memory mapping system electrically coupled to said first memory said receive buffer is positioned In said first memory, said first memory having a size, said size reduced by said memory mapping system, said memory mapping system electrically coupled to said first memory and incorporated in said integrated circuits wherein said local area network circuitry comprises interface controller circuitry to transmit and receive data packaged in said at least one data packet, each data packet of said at least one data packet approximately 1518 bytes, said interface controller circuitry electrically coupled to said first memory and to said at least one data bus, said interface controller circuitry comprises

a transmit buffer configured in said first memory to hold said at least one data packet transmitted to said second host system; and

a receive buffer configured in said first memory to hold said at least one data packet received from said at least one second host system.

2. The integrated circuit of claim 1, wherein said first host system is a personal computer.

3. The integrated circuit of claim 2, wherein said personal computer is based on microprocessors selected from a group consisting of Intel™

286, Intel™

386, Intel™

486, and Intel™

Pentium™

.

4. The integrated circuit of claim 1, wherein said at least one second host system is a personal computer.

5. The integrated circuit of claim 4, wherein said personal computer is based on microprocessors selected from a group consisting of Intel™

286, Intel™

386, Intel™

486, and Intel™

Pentium™

.

6. The integrated circuit of claim 1, wherein said local area network circuitry further comprises

(b3) network controller circuitry electrically coupled to said at least one data bus to coordinate and control communication of data between said first host system and said network, said network controller circuitry electrically coupled to said first memory to access said first memory;

(b4) encoder/decoder circuitry electrically coupled to said network controller circuitry to encode and decode communication between said first host system and said network; and

(b5) driver circuitry and receiver circuitry electrically coupled to said encoder/decoder circuitry to drive communication encoded and decoded by said encoder/decoder circuitry.

7. The integrated circuit of claim 6, wherein said encoder/decoder circuitry conforms to Manchester encoding and decoding protocol.

8. The integrated circuit of claim 1, wherein said local area network circuitry further comprises

(b3) bus interface circuitry to interface with said first host system, said bus interface circuitry electrically coupled to said at least one data bus.

9. The integrated circuit of claim 1, wherein at least one external electrical module can interface with said at least one data bus via said said input and output circuitry.

10. The integrated circuit of claim 1, wherein said at least one external electrical module are electrically erasable, programmable, read only memory.

11. The integrated circuit of claim 1, wherein said first memory further comprises configuration registers to house data packaged in said at least one data packets and said configuration registers to set and to control communication of data packaged in said at least one data packet to and from said local area network circuitry and to control communication of data packaged in said at least one data packet to and from said input and output circuitry.

12. The integrated circuit of claim 1, wherein said network is an Ethernet.

13. The integrated circuit of claim 1, wherein said first memory is random access, non-volatile memory.

14. The integrated circuit of claim 1, wherein said first memory is sufficiently large enough to store data necessary to accommodate a difference between a rate of reception and transmission of data to and from said network.

15. The integrated circuit of claim 1, wherein said at least one data bus is selected from a group consisting of ISA and EISA.

16. The integrated circuit of claim 1, wherein said at least one data bus are at least 8 bits wide.

17. The integrated circuit of claim 1, wherein said local area network circuitry operates at a first dock speed and said input and output circuitry operates at a second dock speed, said local area network further comprising

(b3) an oscillator that oscillates at a predictable speed to create at least one oscillation;

and

(b4) oscillator control circuitry to adjust said at least one oscillation to selectively equal said first clock speed or said second clock speed.

18. The integrated circuit of claim 1, further comprising

(f) power control circuitry to control power to said local area network circuitry and said input and output circuitry, said power control circuitry electrically coupled to said local area network circuitry and to said input and output circuitry.

19. The integrated circuit of claim 1, wherein said transmit buffer is a single block buffer that holds a data packet while said data packet is assembled.

20. The Integrated circuit of claim 1, wherein a beginning of said transmit buffer is defined by a Transmit Page Start Register and an end is defined by a Page Stop Register.

21. The integrated circuit of claim 1, wherein said receive buffer is a circulating buffer ring.

22. The integrated circuit of claim 1, wherein said circulating buffer ring has a beginning and an end, said beginning defined by a Page Start Register and said end defined by a Page Stop Register.

23. The integrated circuit of claim 1, wherein said at least one data packet received from said network is stored into a buffer ring, said at least one data packet is pointed to by a first pointer and said at least one data packet transmitted to said second host system are pointed to by a second pointer.

24. The integrated circuit of claim 23, wherein said first pointer points to a current position and said second pointer points to a boundary position.

25. The integrated circuit of claim 1, wherein said receive buffer is organized in a plurality of pages, each page of said plurality of pages are 256 bytes in length.

26. The integrated circuit of claim 1, such that each data packet of said at least one data packet received by said receive buffer fills up one or more of said 256-byte pages.

27. The integrated circuit of claim 1, wherein said receive buffer has an in-use block of memory, said in-use block having a size that corresponds to an amount of data transmitted or received by said interface controller circuitry.

28. The integrated circuit of claim 1, wherein said memory mapping system maps said receive buffer into a buffer ring.

29. The integrated circuit of claim 1, wherein said memory mapping system has a set of physical address registers and pointers, said pointers controlling data read and data write operations to a buffer ring.

30. The integrated circuit of claim 1, wherein said memory mapping system comprises a memory array storing an to correlate a physical address to an address in said receive buffer.

31. The integrated circuit of claim 30, wherein said physical address is selected from the group consisting of beginning location of said at least one data packet, current packet pointer, and boundary packet pointer.

32. The integrated circuit of claim 1, wherein said memory mapping system is embedded in circuitry.

33. The integrated circuit of claim 1, wherein said memory mapping system operates automatically when said receive buffer is utilized.

34. The integrated circuit of claim 1, wherein said receive and transmit buffers have a variable size.

35. The integrated circuit of claim 1, wherein said at least one data packet is stored in said receive buffer Immediately after one another.

36. The integrated circuit of claim 1, wherein said memory mapping system translates at least one address referencing data in said first memory to at least one address in a logical memory.

37. The integrated circuit of claim 1, wherein said interface controller conforms to a Ethernet standard.

38. The integrated circuit of claim 1, wherein said local area network circuitry, comprises

(b3) a controller electrically coupled to said first memory having access to said first memory;

said controller controlling access to said first memory by said local area network circuitry;

(b4) encoder/decoder electrically coupled to said controller, said encoder/decoder electrically encodes and decodes data transferred to and from said local area network circuitry;

(b5) a driver electrically coupled to said encoder/decoder, said driver to drive signals carrying said data to and from said local area network circuitry; and

(b6) a receiver electrically coupled to said encoder/decoder to receive signals carrying said data to and from said local area network circuitry.

39. The integrated circuit of claim 1, wherein said first memory is random access, non-volatile memory and functions as a data buffer.

40. The integrated circuit of claim 1, comprising an (e) early interrupt system for said local area network circuitry to selectively interrupt said local area network circuitry, said early interrupt system electrically coupled to said local area network circuitry, said early interrupt system comprising:

(e1) receiving circuitry to receive data packaged in said at least one data packet from said network, said at least one data packet having a plurality of data bits, said receiving circuitry electrically coupled to said local area network circuitry; and

(e2) interrupt logic circuitry to receive an interrupt signal from said network to interrupt a transmission of said at least one data packet at a specific bit position, said interrupt logic circuitry electrically coupled to said local area network circuitry;

(e3) said receiving circuitry transfers a portion of said plurality of data bits of said data packet of said at least one data packet already received up to said bit position to be processed and continues to receive said plurality of data bits to at least one said data packet.

41. The integrated circuit of claim 40, wherein said specific bit position is programmable.

42. The integrated circuit of claim 40, wherein said bit position is calculated by subtracting latency interrupt time from a specified number of bytes.

43. The integrated circuit of claim 40, wherein said network is an Ethernet and said network driver is a Ethernet driver.

44. The integrated circuit of claim 40, wherein said interrupt system is enabled via a bit in an network control register, said network control register electrically coupled to said local area network circuitry.

45. The integrated circuit of claim 40, wherein said receiving circuitry initiates a counter, said counter increments fixed time period is eight transmit at least one clock cycle, said counter electrically coupled to said receiving circuitry.

46. The integrated circuit of claim 45, wherein said each clock cycle of said at least one clock cycle equals 100 nano-seconds.

47. The integrated circuit of claim 40, wherein said interrupt signal is transmitted to said receiving circuitry via at least one system data bus, said at least one system data bus electrically coupled to said receiving circuitry.

48. The integrated circuit of claim 40, wherein said specific bit position can be programmed by changing a specified number of bytes with software tools.

49. The integrated circuit of claim 40, wherein said specific bit position can be reprogrammed while said early interrupt system is operating.

50. The integrated circuit of claim 40, wherein said data packet is exactly 1518 bytes in length.

51. The Integrated circuit of claim 1, further comprising

(f) an interrupt system electrically coupled to said local area network circuitry to selectively interrupt said local area network circuitry, said interrupt system comprising

(f1) receiving circuitry to receive an interrupt signal generated by interrupt logic circuitry, said interrupt signal corresponding to an interrupt operation, said receiving circuitry electrically coupled to said local area network circuitry;

and

(f2) timing circuitry that starts incrementing when said interrupt signal is received by said receiving circuitry to determine when said interrupt operation is complete, said timing circuitry electrically coupled to said receiving circuitry.

52. The integrated circuit of claim 51, wherein said timing circuitry stops incrementing when a register is read by a network driver, said timing circuitry is reset after said register is read by said network driver, said network driver electrically coupled to said network.

53. The integrated circuit of claim 51, wherein said interrupt system is enabled via a bit in an network control register.

54. An integrated circuit, comprising

(a) at least one data bus to electrically couple said integrated circuit with a first host system, said at least one data bus transfers data packaged in at least one data package to and from said integrated circuit,

(b) local area network circuitry electrically coupled to said at least one data bus and selectively to a network, said local area network circuitry to electrically couple said integrated circuit and, in turn, said first host system to said network and thereby to at least one second host system via said at least one data bus, said network transfers data packaged in said it least one data packet to and from said local area network circuitry;

(c) input and output circuitry electrically coupled to said at least one data bus, said input and output circuit to electrically couple said integrated circuit and, in turn, said first host system to at least one input/output channel, said input/output channel, selectively electrically coupled to at least one external electrical module, said at least one input/output channel, transfers said data packaged in said at least one data packet to and from said input and output circuitry, wherein said local area network circuitry and said input and output circuitry operate at a first oscillation frequency and at a second oscillation frequency respectively, and further wherein said at least one input/output channel are selected from a group consist of a first serial port interface, a second serial port interface, a parallel port interface, a hard drive, a floppy drive, and any combination thereof;

(d) first memory electrically coupled to said local area network circuitry and to said input and output circuitry and to said at least one data bus, said first memory to store data received and transmitted by said local area network circuitry and said input and output circuitry via said at least one data bus and said network and said at least one input/output channel, said first memory is configurable and has sufficient memory capacity to store more than one data packet of said at least one data packet; and

(e) a clock that oscillates naturally at a clock oscillation and clock generating circuitry to generate the first oscillation frequency and said second oscillation frequency, said clock generating circuitry electrically coupled to said dock and said clock generating circuitry electrically coupled to the local area network circuitry and to the input and output circuitry, wherein said clock generating circuitry comprises phase lock loop circuitry to generate a first clock frequency and a second clock frequency said phase lock loop circuitry having an input electrically coupled to said clock and an output electrically coupled to said local area network circuitry and to said input and output circuitry, further wherein said phase lock loop circuitry having an output comprises

(e1) a phase detector electrically coupled to said clock, said phase detector detects a phase difference associated with said clock oscillation and said output of said phase lock loop circuitry;

(e2) a charge pump electrically coupled to said phase detector, said charge pump adjusts a corresponding voltage associated with said phase difference; and

(e3) a filter electrically coupled to said charge pump to to produce a voltage proportional to said phase difference; and

(e4) a voltage controlled oscillator electrically coupled to said filter to frequency proportional to said voltage, said frequency can be selectively converted into said first clock frequency and into said second clock frequency.

55. The integrated circuit of claim 54, wherein said filter operates in a linear fashion over a wide range of input values.

56. The integrated circuit of claim 54, wherein said phase lock loop circuitry generates oscillations that operate at very high speeds.

57. The integrated circuit of claim 54, wherein said clock generating circuitry comprises a feedback loop to correct errors and to adjust said first clock frequency and said second dock frequency generated by said clock generating circuitry.

58. The integrated circuit of claim 54, wherein said phase detector comprises:

(a) a first D-flip flop having a clock input, a D input, a Q output, and a clear input, said clock input electrically coupled to a first clock signal generated by said clock, said D input is electrically coupled to a first voltage state, said Q output is electrical coupled to said charge pump;

(b) a second D-flip flop having a clock input, a D input, a Q output, and a clear input, said clock input electrically coupled to a second clock signal generated by said voltage controlled oscillator, said D input electrically coupled to said first voltage state;

(c) a NAND gate having first and second inputs and an output, said first and second inputs electrically coupled to said Q outputs of said first and second D-flip flops respectively, said output of said NAND gate is electrically coupled to said clear inputs of said first and second D-flip flops;

(d) a multiplexor having first and second inputs, an output, an S input, said second input electrically coupled to said first reference voltage, said first input electrically coupled to said output of said NAND gate, said output coupled to said clear inputs of said first and second D-flip flops, said S input electrically coupled to said output of said NAND gate; and

(e) a delay line is electrically coupled between said output of said NAND gate and said first input of said multiplexor.