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Switch circuit comprised of logically split switches for parallel transfer of messages and a parallel processor system using the same

  • US 5,754,792 A
  • Filed: 03/19/1993
  • Issued: 05/19/1998
  • Est. Priority Date: 03/19/1992
  • Status: Expired due to Fees
First Claim
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1. A parallel processor system, comprising:

  • a plurality of processors; and

    a plurality of switch circuits each having a plurality of input ports and a plurality of output ports for transferring in parallel a plurality of messages sent from said plurality of processors;

    wherein each of said switch circuits includes;

    a plurality of address modifying circuits provided in correspondence to said plurality of input ports, respectively, for modifying transfer destination addresses which designate transfer destination output ports in said switch circuit, said addresses being contained in said messages inputted through the corresponding input ports, respectively, anda circuit for transferring a message inputted through a given one of said plural input ports to an output port designated by the modified transfer destination address outputted from said address modifying circuit provided in association with said given input port,wherein each of said address modifying circuits includes an arithmetic operation circuit for determining the transfer destination address contained in the message inputted through the input port associated with said address modifying circuit and an address modifying value predetermined for the associated input port by a plurality of logically split switch circuits resulting from a logical partition of said switch circuit, and performing an arithmetic operation on said transfer destination address and said address modifying value to obtain a modified transfer destination address for the one of the logically split switch circuits corresponding to said address modifying circuit.

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