Instruction in a data processing system utilizing extension bits and method therefor

• US 5,754,805 A
• Filed: 03/09/1995
• Issued: 05/19/1998
• Est. Priority Date: 03/31/1993
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Seaton, Robert W. Jr., Gallup, Michael G., Goke, L. Rodney
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US08/401,610
• Time in Patent Office: 1,167 Days
• Field of Search: 395/376, 395/800.01, 364/736.5
• US Class Current: 712/200
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands. The data processing system (55) includes a plurality of instructions which include and utilize an extension bit during execution. In one embodiment, a plurality of instructions, both arithmetic and non-arithmetic, use extension bits for preliminary and non-preliminary instructions in order to accommodate large data widths.

Claims

1. A method of executing an arithmetic instruction in a data processor, comprising the steps of:

receiving the arithmetic instruction the arithmetic instruction being associated with a source operand and a destination operand;

decoding the arithmetic instruction to provide a plurality of control signals;

accessing a first extension bit from a first storage location during execution of the arithmetic instruction, the first extension bit providing a status information value;

accessing a second extension bit from a second storage location during execution of the arithmetic instruction, the second extension bit providing a sign value corresponding to the source operand of the arithmetic instruction;

executing an arithmetic operation in response to the plurality of control signals, both the first extension bit and the second extension bit being used during execution of the arithmetic operation to provide a result the first extension bit and the second extension bit being used in a first manner when the arithmetic instruction is a preliminary instruction and the first extension bit and the second extension bit being used in a second manner when the arithmetic instruction is a non-preliminary instruction;

selectively modifying the first extension bit to store a modified status information value corresponding to the result; and

selectively modifying the second extension bit to store a modified sign value corresponding to the result.

2. The method of claim 1 wherein the arithmetic operation is one of a preliminary addition operation and a non-preliminary addition operation, the preliminary addition operation modifying both the first extension bit and the second extension bit to reflect the result, the non-preliminary addition operation placing both the first extension bit and the second extension bit in a default state.

3. The method of claim 2 wherein the first extension bit is a carry value.

4. The method of claim 2 wherein the preliminary addition operation is a non-saturating addition operation and the non-preliminary addition operation is a saturating addition operation, wherein:

a result of the non-preliminary addition operation is replaced by one of an upper bound and a lower bound when an overflow value corresponding to the result is in an asserted state and the data processing instruction is the non-preliminary addition instruction; and

the result of the data processing operation is not replaced when the overflow value corresponding to the result is in the asserted state and the data processing instruction is the preliminary addition instruction.

5. The method of claim 2 further comprising the steps of:

modifying the source operand using the second extension bit;

adding the source operand to the destination operand to generate the result;

modifying the first extension bit to indicate if the result modified the carry value when the arithmetic operation is the preliminary addition operation; and

placing both the first extension bit and the second extension bit in the default state when the arithmetic operation is the non-preliminary addition operation.

6. The method of claim 5 wherein the source operand is modified using the second extension bit when a bit width of the source operand is a portion of a first data value which has a bit width which is smaller than a bit width a portion of the destination operand.

7. The method of claim 1 wherein the arithmetic operation is one of a preliminary subtraction operation and a non-preliminary subtraction operation, the preliminary subtraction operation modifying both the first extension bit and the second extension bit to reflect the result, the non-preliminary subtraction operation placing both the first extension bit and the second extension bit in a default state.

8. The method of claim 7 wherein the first extension bit is a borrow value.

9. The method of claim 8 further comprising the steps of:

modifying the source operand using the second extension bit;

subtracting the source operand from the destination operand to generate the result;

modifying the first extension bit to indicate if the result modified the borrow value when the arithmetic operation is the preliminary subtraction operation; and

placing both the first extension bit and the second extension bit in a default state when the arithmetic operation is the non-preliminary subtraction operation.

10. A method of executing a comparative instruction in a data processor, comprising the steps of:

receiving the comparative instruction where the comparative instruction is one of a preliminary comparative instruction and a non-preliminary comparative instruction, the comparative instruction being associated with a source operand and a destination operand;

decoding the comparative instruction to provide a first plurality of control signals;

accessing a first extension bit from a first storage location and a second extension bit from a second storage location during execution of the comparative instruction;

comparing the source operand with the destination operand in response to the first plurality of control signals, both the first extension bit and the second extension bit being selectively used during execution of the comparative operation to provide a result; and

selectively modifying the first extension bit and the second extension bit to indicate a current result of the step of comparing the source operand with the destination operand.

11. The method of claim 10 wherein the first extension bit and the second extension bit are selectively modified to indicate a comparative relationship between the destination operand and the source operand used during execution of the comparative instruction.

12. The method of claim 11 further comprising the steps of:

receiving a conditional instruction;

decoding the conditional instruction to provide a second plurality of control signals; and

executing a comparison operation in response to the conditional instruction, the comparison operation using the first extension bit and the second extension bit to indicate a conditional result of the comparison operation.

13. The method of claim 11 wherein the preliminary comparative instruction selectively modifies both the first extension bit and the second extension bit to reflect the result, and wherein the non-preliminary comparative instruction places both the first extension bit and the second extension bit in a default state.

14. The method of claim 11 wherein the first and the second extension bits are selectively modified to indicate one of a following condition:

i) the destination operand is greater than the source operand;

ii) the destination operand is less than the source operand; and

iii) the destination operand is equal to the source operand.

15. The method of claim 11 wherein the first and the second extension bits are both placed in a default state subsequent to the step of comparing the source operand with the destination operand when the comparison instruction is a non-preliminary instruction.

16. A method of executing a comparative instruction in a data processor, comprising the steps of:

receiving the comparative instruction, the comparative instruction being associated with a source operand and a destination operand;

decoding the comparative instruction to provide a first plurality of control signals;

accessing a first extension bit from a first storage location and a second extension bit from a second storage location during execution of the comparative instruction;

comparing the source operand with the destination operand in response to the first plurality of control signals, both the first extension bit and the second extension bit being selectively used during execution of the comparative operation to provide a result; and

selectively modifying the first extension bit and the second extension bit to indicate a current result of the step of comparing the source operand with the destination operand, wherein the first and second extension bits are both placed in a default state subsequent to the step of comparing the source operand with the destination operand when the comparative instruction is a non-preliminary instruction.