Configurable I/O system using logic state arrays

• US 5,754,823 A
• Filed: 02/23/1995
• Issued: 05/19/1998
• Est. Priority Date: 02/23/1995
• Status: Expired due to Fees

• Current Assignee: Datalogic, Inc.
• Original Assignee: Datalogic, Inc.
• Inventors: Yauch, Steven S., Lyman, Richard R., Mudryk, John S. Jr.
• Primary Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US08/393,935
• Time in Patent Office: 1,181 Days
• Field of Search: 395/500, 395/22, 395/21, 395/375, 326/98, 326/21, 326/119, 326/41, 326/16, 326/38, 326/44, 326/47, 326/40, 326/126, 326/125, 326/75, 371/22.3, 371/22.6, 371/62, 340/825.84, 340/825.79, 340/825.03, 340/825.5, 340/825.87, 364/578, 364/490, 364/488, 364/489, 364/716, 365/185.28, 365/189.08, 365/230.03, 365/201, 365/94, 327/17, 327/37
• US Class Current: 710/8
• CPC Class Codes: G05B 19/045 using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
• CPC Class Codes: G05B 2219/21115 Same connector can represent either input or output
• CPC Class Codes: G05B 2219/21139 Input activates directly output and vice versa
• CPC Class Codes: G05B 2219/25268 PLD programmable logic device
• CPC Class Codes: G05B 2219/25413 Interrupt, event, state change triggered

Abstract

A configurable I/O arrangement for a controller has a number of internal and external input/output terminals, each of which are field selected as either an input or an output terminal. Logic functions of the controller are configured for a number of output terminals using up to 32 internal logical states and the states of 32 external physical I/O points. The update timing for each logic circuit is selectable to be synchronized in several different ways: synchronous with an internal event within the controller, synchronous with an event external to the controller, and asynchronous. The I/O arrangement includes a combination of a synchronous latchable input state array, user configurable means for logically combining the output signals of the reading circuits, and means for actuating external devices as a function of the logical combinations of the output signals of the reading circuits.

Claims

1. A configurable I/O system, comprising:

an input state array having a plurality of state variables representing input values;

a logic function means for operating on the plurality of state variables and for providing a logic output signal;

trigger means having a plurality of trigger functions for synchronizing operation of the logic function means with a trigger event;

wherein the trigger means includes a multiplexing means for selecting the trigger event;

wherein the trigger means further includes functional dispatch means for placing a detected preselected input event in a circular event queue and for removing the detected preselected input event from the circular event queue;

wherein the functional dispatch means includes mapping means for mapping the trigger event through a table to the logic means which includes combinatorial logic calculation routine and an initiation means for initiating execution of the combinatorial logic calculation routine; and

wherein the logic function means for operating on the plurality of state variables and for providing a logic output signal includes means for executing a predetermined function in response to the detected preselected input event.

2. The configurable I/O system of claim 1 including an output signal conditioner for conditioning the logic output signal.

3. The configurable I/O system of claim 1 including means for initially configuring the logic function means.

4. The configurable I/O system of claim 1 wherein the trigger means includes means for detecting the preselected input event.

5. The configurable I/O system of claim 1 wherein the logic function means includes a software simulation of a programmable array.

6. The configurable I/O system of claim 5 wherein the programmable array is an array of AND gates and OR gates by means of which outputs can be specified as logical functions of the inputs.

7. The configurable I/O system of claim 1 wherein the input values are state variables which consist of external signals, internally generated signals, counter states, shift register states, and latch states.

8. The configurable I/O system of claim 7 wherein the external signals include a signal which is generated from a presence sensor.

9. The configurable I/O system of claim 8 wherein the signal which is generated from the presence sensor includes a signal generated when an item is in front of an infrared light beam.

10. The configurable I/O system of claim 7 wherein the internally generated signals are internally generated state variables which are provided by a consecutive error counter.

11. A configurable I/O system, comprising

an input state array for receiving a plurality of input signals and having a plurality of elements where each element respectively corresponds to one of said input signals;

a latch array having elements for receiving and storing the states of the respective elements of the input state array;

means for controlling a clock signal provided to the latch array to synchronize operation of an system with the occurrence of the clock signal;

a multi-input AND array;

an AND inverter array having elements for receiving and selectively inverting the elements of the latch means;

an AND input selection array for selectively directing a corresponding bit from the AND inverter array into one of the inputs of the multi-input AND array;

an AND output inverter for selectably inverting the output of the multi-input AND array;

a multi-input OR array;

an OR inverter array having elements for receiving and selectively inverting the elements of the latch means;

an OR input selection array for directing a corresponding bit from the OR inverter array into one of the inputs of the multi-input OR array;

an OR output inverter for selectably inverting the output of the multi-input OR array;

an OR gate for combining the outputs of the AND output inverter and the OR output inverter; and

an output means for outputting the output signal signals for the OR gate.

12. A configurable I/O system, comprising

an input state array having input state variables acted upon by logic functional block arrays;

a first Exclusive OR array for logically combining each respective element of the input state array with the respective elements of an AND invert array;

a first AND array for logically combining each respective elements of the first Exclusive OR array with each respective elements of an And enable array;

a first OR array for logically combining the respective elements of the AND array into a single element;

a first Exclusive-OR invert Array for combining the single element of the OR array with an invert command signal to selectably provide an inverted or non-inverted AND output signal;

a second Exclusive OR array for logically combining each respective element of the input state array with the respective elements of an OR Invert array;

a second AND array for logically combining respective elements of the second Exclusive OR array with respective elements of an OR enable array;

a second OR array for logically combining the respective elements of the second AND array into a single element;

a second Exclusive-OR invert Array for combining the single element of the OR array with an invert command signal to selectably provide an inverted or non-inverted OR output signal and;

an output OR function for logically combining the inverted or non-inverted AND output signal with the inverted or non-inverted OR output signal to provide an output signal.

13. The configurable I/O system of claim 12 including an output signal conditioner for the output signal which alternatively provides a direct channel to an output terminal, shift registers, a pulse circuit, and a latch circuit.

14. The configurable I/O system of claim 12 wherein the output signal is provided to a counter.