Logic synthesis for logic array modules
First Claim
1. A method for the efficient synthesis of logic array modules (LAMs) implementing a logic function said logic function being defined by a multi-level combinational acyclic logic network, inputs to the network being primary inputs and outputs from the network being primary outputs, said method comprising the steps of:
- logically partitioning vertically the logic network to define a plurality of logic segments wherein each output of a logic segment can potentially be implemented in a single logic array module;
logically partitioning horizontally the plurality of logic segments to reduce the size of the segments to a size that can be efficiently implemented as a logic array module; and
generating a symbolic representation in a logic array module table of an internal structure of the logic array module based on the horizontally partitioned logic segments,wherein in the step of logically partitioning vertically, a physical limit is imposed on the number of products in the logic array module and further comprising the step of estimating an upper bound on the number of products needed to implement said output, where the function of said output is represented as a reduced ordered binary decision diagram and where the number of products of a node in the diagram is not more than the sum of the estimates of the number of products for its inputs and where the number of products at the inputs of nodes without predecessors is zero.
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Abstract
A general approach to the synthesis of logic array modules (LAMs) is used to implement a multilevel combinational acyclic network. The network consists of abstract gates, which perform primitive logic functions and nets to connect them. The inputs to the entire network are called the primary inputs and the outputs of the entire network are the primary outputs. The first step in the synthesis of the LAMs used to implement the network is to partition the network vertically to define a plurality of logic segments wherein each output of a logic segment can potentially be implemented in a single logic array module. The second step is to partition horizontally the plurality of logic segments to reduce the size of the segments to a size that can efficiently be implemented as a logic array module. A symbolic representation is generated in a logic array module table of an internal structure of the logic array module based on the horizontally partitioned logic segments.
19 Citations
10 Claims
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1. A method for the efficient synthesis of logic array modules (LAMs) implementing a logic function said logic function being defined by a multi-level combinational acyclic logic network, inputs to the network being primary inputs and outputs from the network being primary outputs, said method comprising the steps of:
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logically partitioning vertically the logic network to define a plurality of logic segments wherein each output of a logic segment can potentially be implemented in a single logic array module; logically partitioning horizontally the plurality of logic segments to reduce the size of the segments to a size that can be efficiently implemented as a logic array module; and generating a symbolic representation in a logic array module table of an internal structure of the logic array module based on the horizontally partitioned logic segments, wherein in the step of logically partitioning vertically, a physical limit is imposed on the number of products in the logic array module and further comprising the step of estimating an upper bound on the number of products needed to implement said output, where the function of said output is represented as a reduced ordered binary decision diagram and where the number of products of a node in the diagram is not more than the sum of the estimates of the number of products for its inputs and where the number of products at the inputs of nodes without predecessors is zero. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for the efficient synthesis of logic array modules (LAMs) implementing a logic function, said logic function being defined by a multi-level combinational acyclic logic network inputs to the network being primary inputs and outputs from the network being primary outputs, said method comprising the steps of:
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logically partitioning vertically the logic network to define a plurality of logic segments wherein each output of a logic segment can potentially be implemented in a single logic array module; logically partitioning horizontally the plurality of logic segments to reduce the size of the segments to a size that can be efficiently implemented as a logic array module; and generating a symbolic representation in a logic array module table of an internal structure of the logic array module based on the horizontally partitioned logic segments, wherein in the step of logically partitioning horizontally, a physical limit is imposed of the number of outputs of a logic array module and a physical limits is imposed on the total number of products needed to implement all outputs of a logic array module, and wherein in the step of horizontally partitioning the vertical segment horizontally partitions the segment into a plurality of logic array modules such that each horizontal segment satisfies the physical limits, wherein, in the step of logically partitioning horizontally, the horizontal partitioning of the segment is performed by partitioning nodes of a derived graph, which graph is derived by forming a node for each output of the segment and by forming an edge in the graph for each gate in the segment, the edge connecting to each node for which there is a directed path in the logic of the segment from the gate to the output corresponding to that node, each edge having an associated partitioning cost equal to a cost of duplicating the gate in the segment.
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9. A method for the efficient synthesis of logic array modules (LAMs) implementing a logic function, said logic function being defined by a multi-level combinational acyclic logic network, inputs to the network being primary inputs and outputs from the network being primary outputs, said method comprising the steps of:
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logically partitioning vertically the logic network to define a plurality of logic segments wherein each output of a logic segment can potentially be implemented in a single logic array module; logically partitioning horizontally the plurality of logic segments to reduce the size of the segments to a size that can be efficiently implemented as a logic array module; and generating a symbolic representation in a logic array module table of an internal structure of the logic array module based on the horizontally partitioned logic segment, wherein in the step of logically partioning horizontally, a physical limit is imposed on the number of outputs of a logic array module and a physical limits is imposed on the total number of products needed to implement all outputs of a logic array module, and wherein in the step of horizontally partitioning the vertical segment horizontally partitions the segment into a plurality of logic array modules such that each horizontal segment satisfies the physical limits, wherein, in the step of logically partioning horizontally each horizontal segment which satisfies the limits is horizontally partitioned into two horizontal segments while estimating a delay and area of a logic array module implementation of each of the horizontal segments, and using estimates of delay and area to determine if the newly created horizontal segments are smaller or faster than the unpartitioned segment, and repeating this process as long as improvements in area or delay can be realized. - View Dependent Claims (10)
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Specification