CAD and simulation system for targeting IC designs to multiple fabrication processes

• US 5,754,826 A
• Filed: 08/04/1995
• Issued: 05/19/1998
• Est. Priority Date: 08/04/1995
• Status: Expired due to Term

• Current Assignee: Arm Incorporated (SoftBank Group Corp.)
• Original Assignee: Synopsys Incorporated
• Inventors: Reyneri, Justin M., Gamal, Abbas El, Marple, David P.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Fiul, Dan
• Application Number:
  US08/511,172
• Time in Patent Office: 1,019 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 395/500
• US Class Current: 703/14
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

Using the present invention, only a single design and development process needs to be conducted for ICs fabricated using a number of different fabrication processes. In one embodiment of this process, the IC is first designed on a CAD system using a generic Cell Based Architecture (CBA) library. This generic CBA library represents several libraries for different process technologies. The resulting generic design is then simulated and verified using best and worst case timing delays and other parameters which are derived from a combination of the various technologies. Hence, only one design need be created and simulated. Generic design rule and parasitic parameters are then used to optimize the placement and routing of the generic design. The post-layout generic design is then simulated and verified using performance characteristics determined by a combination of the technologies. The accepted, generic post-layout design is then ported for each intended fabrication process to create the mask patterns associated with each fabrication process.

Claims

1. A method for developing an integrated circuit for being fabricated using two or more process technologies, said method comprising the steps of:

providing a generic library of generic macrocells, each of said generic macrocells representing process specific macrocells formed using two or more different process technologies;

designing a generic circuit using said generic macrocells and a generic alignment grid;

simulating said generic circuit using performance characteristics of said process specific macrocells to verify that said generic circuit, when ported to any of said process technologies, would work for its intended purpose;

porting said generic circuit to said two or more process technologies by substituting said generic macrocells in said generic circuit with process specific macrocells and substituting said generic alignment grid with a process specific alignment grid, wherein each generic macrocell location is mapped from its generic reference location on said generic alignment grid to a corresponding process specific macrocell reference location on said process specific alignment grid; and

creating a set of masks for each of said processes to enable said integrated circuit to be manufactured using said two or more process technologies.

2. The method of claim 1 further comprising the step of conducting a generic macrocell placement and routing routine on said generic circuit to optimize placement of said generic macrocells and metallization routing between said generic macrocells with respect to said generic alignment grid, and wherein said step of simulating said generic circuit comprises:

simulating said generic circuit prior to said step of conducting placement and routing, and then simulating said generic circuit after said step of conducting placement and routing.

3. The method of claim 2 wherein simulating said generic circuit after said step of conducting placement and routing comprises the step of:

determining a minimum delay and a maximum delay of said generic circuit using said performance characteristics of said process specific macrocells to determine performance delays under both worst case and best case conditions.

4. The method of claim 1 wherein said generic circuit is formed, at least in part, by interconnecting elements in a gate array.

5. The method of claim 4 wherein said gate array is comprised of an array of cells, where said cells comprise compute sections and drive sections, said drive sections containing transistors which have a higher current handling capability than transistors within said compute sections.

6. The method of claim 1 wherein said step of designing a generic circuit comprises the steps of:

creating a logic design by identifying the logic functions needed to be performed by said integrated circuit;

simulating said logic design to verify its intended function; and

using said generic macrocells to replace said logic functions to design said generic circuit.

7. The method of claim 1 wherein said step of simulating said generic circuit comprises the steps of:

selecting a maximum delay, a minimum delay, and an average delay for process specific macrocells conforming to said generic macrocells in said generic circuit; and

simulating the performance of said generic circuit using said maximum delay, said minimum delay, and said average delay to emulate the final integrated circuit under maximum, minimum, or average delay conditions.

8. The method of claim 1 further comprising the step of conducting a generic macrocell placement and routing routine on said generic circuit to optimize placement of said generic macrocells and metallization routing between said generic macrocells with respect to said generic alignment grid.

9. The method of claim 8 wherein said generic macrocells and said process specific macrocells maintain the same central origin relative to their respective alignment grids.

10. The method of claim 9 wherein said generic circuit is formed, at least in part, by interconnecting elements in a gate array.

11. The method of claim 10 wherein said generic circuit further includes a custom block which is not a portion of said gate array.

12. The method of claim 1 further comprising the step of performing a design rule check to determine if the final design of each process specific circuit violates any design rules for that process.

13. The method of claim 1 wherein said generic alignment grid corresponds to a generic metallization routing grid, and said process specific alignment grid corresponds to a process specific metallization routing grid.

14. A computer readable storage medium containing a software program for aiding in the development of an integrated circuit for being fabricated using two or more process technologies, said program comprising:

a generic library containing generic macrocells which correspond to logical functions;

a process specific library containing process specific macrocells corresponding to generic macrocells in said generic library;

a set of generic design rules and parameters for placing and routing generic macrocells on a generic alignment grid to carry out performance functions specified by a user of said software;

conversion software for transforming a generic circuit design to a particular process specific circuit design enabling the generic circuit design to be fabricated with a particular process, said generic circuit design comprising said generic macrocells located on said generic alignment grid and being interconnected to carry out desired logical functions, said process specific circuit design comprising said process specific macrocells located on a process specific alignment grid and being interconnected to carry out said desired logical functions, said conversion software substituting said generic macrocells in said generic circuit design with process specific macrocells and substituting said generic alignment grid with a process specific alignment grid, wherein each generic macrocell location is mapped from its generic reference location on said generic alignment grid to a corresponding process specific macrocell reference location on said process specific alignment grid; and

performance parameters for said process specific macrocells for computation of estimated delay characteristics when said generic circuit is fabricated using said two or more process technologies, enabling the generic circuit design to be simulated and verified to determine whether the final integrated circuit will work for its intended purpose when fabricated using said two or more process technologies.

15. The computer readeable storage medium of claim 14 wherein a logic synthesis program interacts with said generic library to create a generic hardware design which carries out said performance functions specified by the user of said software.

16. The computer readeable storage medium of claim 14 further comprising a simulation program for simulating a generic circuit design after being placed and routed on said generic alignment grid to determine, at least, a worst case performance of said generic circuit design when ported to said two or more process technologies.

17. The computer readeable storage medium of claim 14 wherein said generic library and said process specific library contain macrocells formed using a cell based architecture.

18. The computer readeable storage medium of claim 17 where said cell based architecture is a gate array consisting of an array of basic cells, where each basic cell includes a compute section and a drive section, said drive section having transistors which are larger than transistors in said compute section.