High density ferroelectric memory with increased channel modulation and double word ferroelectric memory cell for constructing the same

• US 5,757,042 A
• Filed: 06/14/1996
• Issued: 05/26/1998
• Est. Priority Date: 06/14/1996
• Status: Expired due to Term

• Current Assignee: Radiant Technologies, Inc. (Salesforce.com, Inc.)
• Original Assignee: Radiant Technologies, Inc. (Salesforce.com, Inc.)
• Inventors: Evans, Joseph T. Jr., Womack, Richard
• Primary Examiner(s): Ngo , Ngan V.
• Application Number:
  US08/663,675
• Time in Patent Office: 711 Days
• Field of Search: 257/295, 257/314, 257/352, 257/368
• US Class Current: 257/295
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A memory based on a ferroelectric FET, the ferroelectric FET includes a gate electrode, a layer of ferroelectric material, layer of semiconducting material, a source electrode and a drain electrode. The layer of ferroelectric material is sandwiched between the gate electrode and the layer of semiconducting material, the source and drain electrodes being in contact with the layer of semiconducting material and spaced apart from one another. The memory includes a circuit for setting the ferroelectric FET to one of two states. The first state is set by applying a first voltage to the source and drain electrodes and a second voltage to the gate electrode. The second state is set by applying a third voltage to the gate and drain electrodes and fourth voltage to the source electrode. This arrangement reduces the number of pass transistors needed per ferroelectric FET to one plus a simple pulsing circuit that must be included with each word of memory.

Claims

1. A memory comprising a ferroelectric FET, said ferroelectric FET comprising a gate electrode, a layer of ferroelectric material, layer of semiconducting material, a source electrode and a drain electrode, said layer of ferroelectric material being sandwiched between said gate electrode and said layer of semiconducting material, said source and drain electrodes being in contact with said layer of semiconducting material and spaced apart from one another;

a circuit for setting said ferroelectric FET to one of two states, said first state being set by applying a first voltage to said source and drain electrodes and a different voltage to said gate electrode, and said second state being set by applying a second voltage to said gate and drain electrodes and different voltage to said source electrode.

2. A circuit for storing a word, said circuit comprising:

N single bit memory cells, wherein N>

2, each of said single bit memory cells comprising a pass transistor and a ferroelectric FET, said pass transistor including a pass gate and first and second terminals, said pass transistor providing a conducting path between said first and second terminals in response to said pass gate being coupled to a predetermined potential, all of said pass gates being connected to a common word line,

said ferroelectric FET comprising a gate electrode, a layer of ferroelectric material, layer of semiconducting material, a source electrode and a drain electrode, said layer of ferroelectric material being sandwiched between said gate electrode and said layer of semiconducting material, said source and drain electrodes being in contact with said layer of semiconducting material, wherein said drain electrode of said ferroelectric FET is connected to said first terminal of said pass transistor; and

a write circuit for sequentially setting one of said ferroelectric FETs to a first state by holding said source and drain electrodes of said ferroelectric FET at a first potential and said gate electrode at a potential different from said first potential, and then setting said ferroelectric FETs to a second state or a third state depending on the potential on said second terminal of said pass transistor, said second state being written by holding said source and drain electrode at the same potential and said gate electrode at a different potential, and said third state being written by holding said gate and drain electrode at a the same potential and said source electrode at a different potential.

3. The circuit of claim 2 wherein said ferroelectric layer in each of said single bit memory cells comprises a portion of a common ferroelectric layer that is shared by all of said ferroelectric FETs, each of said ferroelectric FETs occupying a portion of said common ferroelectric layer with a portion of said ferroelectric layer between said ferroelectric FETs remaining unoccupied, and wherein each of said gate electrodes in said ferroelectric FETs is connected to a common gate electrode.

4. A circuit for storing two words, said circuit comprising:

N two bit memory cells, wherein N>

2, each of said two bit memory cells comprising first and second pass transistors and a two bit ferroelectric storage cell, each of said pass transistors including a pass gate and first and second terminals, said pass transistor providing a conducting path between said first and second terminals in response to said pass gate being coupled to a predetermined potential; and

said two bit ferroelectric storage cell comprising a gate electrode, a layer of ferroelectric material, layer of semiconducting material, first and second source electrodes and first and second drain electrodes, said layer of ferroelectric material being sandwiched between said gate electrode and said layer of semiconducting material, said source and drain electrodes being in contact with said layer of semiconducting material, wherein said first drain electrode of said two bit ferroelectric storage cell is connected to said first terminal of said first pass transistor and said second drain electrode of said two bit ferroelectric storage cell is connected to said first terminal of said second pass transistor;

wherein all of said gate electrodes in said circuit are connected to a common gate electrode, all of said first source electrodes are connected to a first common source electrode, and all of said second source electrodes are connected to a second common source electrode.

5. The circuit of claim 4 wherein said ferroelectric layer in each of said two bit ferroelectric storage cells comprises a portion of a common ferroelectric, each of said ferroelectric layers of said two bit ferroelectric storage cells being a portion of said common ferroelectric layer with a portion of said ferroelectric layer between said ferroelectric FETs being unoccupied.

6. A memory comprising:

a plurality of word storage cells organized into a rectangular array including a plurality of columns and rows, each of said word storage cells comprising;

a plurality of single bit memory cells, each of said single bit memory cells comprising a pass transistor and a ferroelectric storage element, said pass transistor including a pass gate and first and second terminals, said pass transistor providing a conducting path between said first and second terminals in response to said pass gate being coupled to a predetermined potential; and

said ferroelectric storage element comprising a gate electrode, a layer of ferroelectric material, layer of semiconducting material, a source electrode and a drain electrode, said layer of ferroelectric material being sandwiched between said gate electrode and said layer of semiconducting material, said source and drain electrodes being in contact with said layer of semiconducting material, wherein said drain electrode of said ferroelectric storage element is connected to said first terminal of said pass transistor, and wherein all of said gate electrodes in said word storage cell are connected to a common gate electrode and all of said source electrodes in said word storage cell are connected to a common source,

wherein all of said common gate electrodes in each one of said columns are connected electrically to a column electrode corresponding to that column and all of said pass gates in each of said rows are connected electrically to a row electrode corresponding to that row.

7. The memory of claim 6 further comprising:

means for receiving an address comprising a plurality of bits divided into first and second groups of bits;

means for selecting one of said column electrodes, said selection depending on said first group of bits; and

means for selecting one of said row electrodes, said selection depending on said second group of bits.