Surface mount and flip chip technology for total integrated circuit isolation

• US 5,757,081 A
• Filed: 02/20/1996
• Issued: 05/26/1998
• Est. Priority Date: 05/05/1994
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, Ho, Yueh-Se, Owyang, King, Chang, Mike F., Dun, Jowei
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US08/603,512
• Time in Patent Office: 826 Days
• Field of Search: 257/684, 257/706-7, 257/501-2, 257/510, 257/513, 257/675, 257/705-6, 257/707, 257/712-713, 257/719, 257/778
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/3738 Semiconductor materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: Y10S 148/135 Removal of substrate
• CPC Class Codes: Y10S 438/928 Front and rear surface processing
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

Claims

1. An integrated circuit comprising:

A semiconductor substrate having a principal surface;

a plurality of semiconductor devices formed in the substrate;

a pattern of conductive lines formed overlying the principal surface and in electrical contact with the devices;

a thermally conductive plate affixed to the principal surface of the substrate and overlying the pattern of conductive lines and overlying the plurality of semiconductor devices, the plate being electrically insulated from the pattern of conductive lines, wherein the plate provides mechanical support for the substrate and the pattern of conductive lines, and whereby the plate is a part of the completed integrated circuit;

a plurality of trenches filled with dielectric material and extending from the principal surface of the substrate through the substrate and to an opposing backside surface thereof, wherein the trenches dielectrically isolate the semiconductor devices from one another;

a plurality of through holes defined in the plate; and

a plurality of electrical contacts, one electrical contact extending through each of the through holes and being in electrical contact with one of the semiconductor devices.

2. The integrated circuit of claim 1, further comprising a plurality of electrically conductive contacts formed on the backside surface of the substrate, each conductive contact being in contact with a selected portion of the backside surface as defined by the plurality of trenches.

3. The integrated circuit of claim 1, wherein a thickness of the substrate is less than about 50 micrometers.

4. The integrated circuit of claim 1, further comprising an overlying insulating layer at least partially overlying the pattern of conductive lines, and further comprising a second pattern of conductive lines juxtaposed to the plate and in electrical contact with the first pattern.

5. The integrated circuit of claim 1, further comprising a protective layer overlying the substrate, and wherein the plate is affixed to the protection layer.

6. The integrated circuit of claim 1, wherein the substrate defines a plurality of conductive vias extending from the principal surface thereof to the backside surface thereof, each via being in electrical contact on the principal surface with a portion of the pattern of conductive lines, and each via forming an electrical contact on the backside surface.

7. The integrated circuit of claim 6, wherein the electrical contacts on the backside surface are each a post extending from the backside surface.

8. An integrated circuit comprising:

a semiconductor substrate having a principal surface;

a plurality of semiconductor devices formed in the substrate;

a pattern of conductive lines formed overlying the principal surface and in electrical contact with the devices;

a thermally conductive plate affixed to the principal surface of the substrate and overlying the pattern of conductive lines and overlying the plurality of semiconductor devices, the plate being insulated from the pattern of conductive lines, wherein the plate provides mechanical support for the substrate and the pattern of conductive lines, and whereby the plate is a part of the completed integrated circuit;

a plurality of insulated trenches extending from the principal surface of the substrate through the substrate and to an opposing backside surface thereof;

a plurality of through holes defined in the plate; and

a plurality of electrical contacts, one electrical contact extending through each of the through holes and being in electrical contact with one of the semiconductor devices.