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Semiconductor device having a test mode setting circuit

  • US 5,757,202 A
  • Filed: 01/29/1996
  • Issued: 05/26/1998
  • Est. Priority Date: 09/22/1993
  • Status: Expired due to Fees
First Claim
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1. A semiconductor device having a normal operation mode and a test operation mode including a plurality of testing operations, the semiconductor device comprising:

  • a plurality of input terminals, the semiconductor device for receiving data supplied through said plurality of input terminals, and for performing a normal operation in said normal operation mode, and, in said test operation mode a testing operation selected from said plurality of testing operations in accordance with a testing operation designating data supplied through said plurality of input terminals;

    a high voltage detection circuit, connected to a predetermined input terminal of said plurality of input terminals, for generating a detection signal when a mode switching signal having a high voltage higher than a power supply voltage is supplied to a first input terminal;

    a pulse generating circuit, connected to receive said detection signal, for generating a pulse during a predetermined period of time starting when said mode switching signal is applied to said predetermined input terminal;

    a plurality of latch circuits activated by an active level of said detection signal for temporarily holding said testing operation designating data as a whole; and

    a plurality of gate circuits, each having an input connected to a corresponding input terminal of said plurality of input terminals, and activated by both an active level of said pulse and said active level of said detection signal, so as to pass a logic level on said corresponding input terminal to a corresponding latch circuit of said plurality of latch circuits and to cause said corresponding latch circuit to hold said logic level on said corresponding input terminal during said predetermined period of time, so that said plurality of latch circuits temporarily hold said testing operation designating data as a whole during a period of time in which said high voltage continues to be supplied to said predetermined input terminal, so that a test is performed based on said testing operation designating data held in said plurality of latch circuits and data applied to said plurality of input terminals after lapse of said predetermined period of time.

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