Semiconductor device having a test mode setting circuit
First Claim
1. A semiconductor device having a normal operation mode and a test operation mode including a plurality of testing operations, the semiconductor device comprising:
- a plurality of input terminals, the semiconductor device for receiving data supplied through said plurality of input terminals, and for performing a normal operation in said normal operation mode, and, in said test operation mode a testing operation selected from said plurality of testing operations in accordance with a testing operation designating data supplied through said plurality of input terminals;
a high voltage detection circuit, connected to a predetermined input terminal of said plurality of input terminals, for generating a detection signal when a mode switching signal having a high voltage higher than a power supply voltage is supplied to a first input terminal;
a pulse generating circuit, connected to receive said detection signal, for generating a pulse during a predetermined period of time starting when said mode switching signal is applied to said predetermined input terminal;
a plurality of latch circuits activated by an active level of said detection signal for temporarily holding said testing operation designating data as a whole; and
a plurality of gate circuits, each having an input connected to a corresponding input terminal of said plurality of input terminals, and activated by both an active level of said pulse and said active level of said detection signal, so as to pass a logic level on said corresponding input terminal to a corresponding latch circuit of said plurality of latch circuits and to cause said corresponding latch circuit to hold said logic level on said corresponding input terminal during said predetermined period of time, so that said plurality of latch circuits temporarily hold said testing operation designating data as a whole during a period of time in which said high voltage continues to be supplied to said predetermined input terminal, so that a test is performed based on said testing operation designating data held in said plurality of latch circuits and data applied to said plurality of input terminals after lapse of said predetermined period of time.
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Accused Products
Abstract
In a semiconductor device having "N" input terminals, a high voltage for a mode switching is applied to a first input terminal, and mode setting information is supplied to the other input terminals. A latch circuit holds the mode setting information supplied during a predetermined period of time starting from application of the high voltage to the first input terminal, during a period of time in which the high voltage continues to be supplied to the first input terminal. Thus, a test is performed on the basis of the mode switching instruction held in the latch circuit and data applied to the other input terminals. On the other hand, if the high voltage is disconnected, the latch circuit is reset.
14 Citations
20 Claims
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1. A semiconductor device having a normal operation mode and a test operation mode including a plurality of testing operations, the semiconductor device comprising:
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a plurality of input terminals, the semiconductor device for receiving data supplied through said plurality of input terminals, and for performing a normal operation in said normal operation mode, and, in said test operation mode a testing operation selected from said plurality of testing operations in accordance with a testing operation designating data supplied through said plurality of input terminals; a high voltage detection circuit, connected to a predetermined input terminal of said plurality of input terminals, for generating a detection signal when a mode switching signal having a high voltage higher than a power supply voltage is supplied to a first input terminal; a pulse generating circuit, connected to receive said detection signal, for generating a pulse during a predetermined period of time starting when said mode switching signal is applied to said predetermined input terminal; a plurality of latch circuits activated by an active level of said detection signal for temporarily holding said testing operation designating data as a whole; and a plurality of gate circuits, each having an input connected to a corresponding input terminal of said plurality of input terminals, and activated by both an active level of said pulse and said active level of said detection signal, so as to pass a logic level on said corresponding input terminal to a corresponding latch circuit of said plurality of latch circuits and to cause said corresponding latch circuit to hold said logic level on said corresponding input terminal during said predetermined period of time, so that said plurality of latch circuits temporarily hold said testing operation designating data as a whole during a period of time in which said high voltage continues to be supplied to said predetermined input terminal, so that a test is performed based on said testing operation designating data held in said plurality of latch circuits and data applied to said plurality of input terminals after lapse of said predetermined period of time. - View Dependent Claims (2, 3, 4)
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5. A semiconductor device comprising:
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a plurality of input terminals; a high voltage detection circuit, connected to a predetermined input terminal of said plurality of input terminals, for generating a detection signal when a mode switching signal having a high voltage higher than a power supply voltage is supplied to a first input terminal; a pulse generating circuit, connected to receive said detection signal, for generating a pulse having a predetermined active level period when a predetermined signal is applied to said predetermined input terminal; a plurality of data latch circuits each activated by an active level of said detection signal for temporarily holding a received signal; and a plurality of gate circuits, each having an input connected to a corresponding input terminal of said plurality of input terminals, and activated by said active level of said pulse and said active level of said detection signal, so as to pass a logic level on said corresponding input terminal to a corresponding data latch circuit of said plurality of data latch circuits and to cause said corresponding data latch circuit to hold said logic level on said corresponding input terminal during said predetermined period of time, so that a plurality of logic levels temporarily held in said plurality of data latch circuits during a period of time in which said predetermined signal continues to be supplied to said predetermined input terminal, form an operation designation data, after lapse of said predetermined period of time, the semiconductor device executing an operation designated from a plurality of operations in accordance with said operation designation data held in said plurality of data latch circuits, and processing data supplied through said plurality of input terminals, in said operation being executed. - View Dependent Claims (6, 7, 8)
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9. A semiconductor device comprising:
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"N" input terminals (where "N" is an integer larger than
1), a high voltage, which is higher than a power supply voltage and which instructs to set the semiconductor device into a test mode, being applied to a first input terminal of said "N" input terminals;high voltage detection means connected to said first input terminal for generating a detection signal when said high voltage is supplied to said first input terminal; pulse generation means responding to said detection signal from said high voltage detection means to generate a pulse having a pulse width corresponding to a predetermined period of time starting from a moment said high voltage is supplied to said first input terminal; and holding means, connected to a selected input terminal of said "N" input terminals other than said first input terminal, and controlled by said detection signal and said pulse, for holding a mode setting information supplied to said selected input terminal during said predetermined period of time, said mode setting information being held by said holding means during a period of time in which said high voltage continues to be supplied to said first input terminal, so that a test is performed based on said mode setting information held in said holding means and data applied to said "N" input terminals after lapse of said predetermined period of time. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification