Digitally controlled programmable attenuator

• US 5,757,220 A
• Filed: 12/23/1996
• Issued: 05/26/1998
• Est. Priority Date: 12/23/1996
• Status: Expired due to Term

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Murden, Franklin M., Moreland, Carl W.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LE, DINH THANH
• Application Number:
  US08/772,359
• Time in Patent Office: 519 Days
• Field of Search: 327/306, 327/530, 327/308, 333/81 R
• US Class Current: 327/308
• CPC Class Codes: H03G 1/0088 using discontinuously variable devices, e.g. switch-operated
• CPC Class Codes: H03H 11/24 Frequency-independent attenuators

Abstract

A digitally controlled programmable attenuator maintains tight phase matching between attenuated signals over wide ranges of frequencies and power levels regardless of the selected attenuation level. This is achieved with a multi-tap ladder network that sets a desired tap-to-tap dB step-size, a plurality of unity gain digitally switched voltage-to-voltage buffers that are connected between the respective taps and a common output, and a fixed gain stage that sets the attenuator'"'"'s overall gain/attenuation. The buffers maintain a high and substantially constant impedance whether turned on or turned off. Phase matching within 0.2° at frequencies up to 300 MHz for 30 dB of gain variation has been realized. The buffers can be implemented with complementary bipolar or BiCMOS processes

Claims

1. A digitally controlled programmable attenuator, comprising:

a multi-tap resistive ladder network that attenuates an analog voltage signal to establish a plurality of voltage signals at its taps having different attenuation levels;

a plurality of voltage-to-voltage buffers that are connected between the respective taps and a common output, said buffers having respective digital inputs for receiving a digital signal that turns on one of said buffers so that the voltage signal at its tap is switched through to the common output while the other buffers are held off, each said buffer presenting a substantially constant impedance, whether on or off, at its tap so that the voltage signals switched through said buffers to said common output are approximately phase matched; and

a fixed gain stage that amplifies the voltage signal at the common output by a fixed gain level to set the attenuator'"'"'s overall gain range.

2. The digitally controlled programmable attenuator of claim 1, wherein each buffer comprises:

an input stage that is always on such that it presents an approximately constant impedance at its tap so that a total impedance of the programmable attenuator, and thus a phase of the voltage signal switched through to the common output is approximately constant regardless of which buffer is switched on; and

an output stage that turns on and off in response to the digital signal at said digital input to selectively switch the voltage signal at the buffer'"'"'s tap through to the common output.

3. The digitally controlled programmable attenuator of claim 2, wherein said input stage conducts a bias current and comprises:

a current regulation circuit that reduces the bias current to reduce power consumption when the buffer is off.

4. A digitally controlled programmable attenuator, comprising:

a multi-tap resistive ladder network that attenuates an analog voltage signal to establish a plurality of voltage signals at its taps having different attenuation levels;

a plurality of buffers that are connected between the respective taps and a common output, said buffers having respective digital inputs for receiving a digital signal that turns on one of said buffers so that the voltage signal at its tap is switched through to the common output while the other buffers are held off, said buffers presenting a substantially constant impedance at their respective taps so that the voltage signals switched through said buffers to said common output are approximately phase matched, each said buffer comprising,

an input stage that is always on such that it presents an approximately constant impedance at its tap so that a total impedance of the programmable attenuator, and thus a phase of the voltage signal switched through to the common output is approximately constant regardless of which buffer is switched on, and

an output stage that turns on and off in response to the digital signal at said digital input to selectively switch the voltage signal at the buffer'"'"'s tap through to the common output, said input and output stages each comprise a complementary bipolar class A-B push-pull stage and said output stage further comprises a switching circuit for turning its push-pull stage on and off in response to the digital signal; and

a fixed gain stage that amplifies the voltage signal at the common output by a fixed gain level to set the attenuator'"'"'s overall gain range.

5. The digitally controlled programmable attenuator of claim 4, wherein said input stage'"'"'s push-pull stage conducts a bias current, said input stage further comprising a current regulation circuit that reduces the bias current when the buffer is turned off to a level that is sufficiently large to keep the push-pull stage on and maintain the constant impedance but would not be sufficient to sustain the performance of the stage were the buffer turned on.

6. A digitally controlled programmable attenuator, comprising:

a multi-tap resistive ladder network that attenuates an analog voltage signal to establish a plurality of voltage signals at its taps having different attenuation levels;

a plurality of buffers that are connected between the respective taps and a common output, said buffers having respective digital inputs for receiving a digital signal that turns on one of said buffers so that the voltage signal at its tap is switched through to the common output while the other buffers are held off, said buffers presenting a substantially constant impedance at their respective taps so that the voltage signals switched through said buffers to said common output are approximately phase matched, each said buffer comprising,

an input stage having an input bipolar emitter-follower that is biased such that it is always on and buffers the voltage signal at its tap through to an internal node said input stage presenting an approximately constant impedance at its tap so that a total impedance of the programmable attenuator, and thus a phase of the voltage signal switched through to the common output is approximately constant regardless of which buffer is switched on, and

an output stage that turns on and off in response to the digital signal at said digital input to selectively switch the voltage signal at the buffer'"'"'s tap through to the common output, said output stage comprising,

an output bipolar emitter-follower that selectively buffers the voltage signal at said internal node through to the common output,

a control switch that turns said output bipolar emitter-follower on and off in response to said digital signal, and

a CMOS switch that switches in opposition to said control switch to apply the voltage signal at said internal node to said output bipolar emitter-follower when it is turned on; and

a fixed gain stage that amplifies the voltage signal at the common output by a fixed gain level to set the attenuator'"'"'s overall gain range.

7. A digitally controlled programmable attenuator, comprising:

a multi-tap resistive ladder network that attenuates an analog voltage signal to establish a plurality of voltage signals at its taps having different attenuation levels;

a plurality of buffers that are connected between the respective taps and a common output, said buffers having respective digital inputs for receiving a digital signal that turns on one of said buffers so that the voltage signal at its tap is switched through to the common output while the other buffers are held off, said buffers presenting a substantially constant impedance at their respective taps so that the voltage signals switched through said buffers to said common output are approximately phase matched, each said buffer comprising

a bipolar emitter-follower that selectively buffers the voltage signal at said tap through to said common output, said emitter-follower'"'"'s collector-base capacitance providing the buffer'"'"'s constant impedance seen at said tap when said emitter-follower is turned on;

a control switch that turns said bipolar emitter-follower on and off in response to said digital signal;

a first CMOS switch that switches in opposition to said control switch to apply the voltage signal at said tap to said bipolar emitter-follower when it is turned on;

a bipolar load transistor having a common base-emitter connection; and

a second CMOS switch that switches in opposition to said first CMOS switch so that when said emitter-follower is turned off the load transistor'"'"'s collector-base capacitance is seen at said tap to maintain the buffer'"'"'s constant impedance; and

a fixed gain stage that amplifies the voltage signal at the common output by a fixed gain level to set the attenuator'"'"'s overall gain range.

8. A digitally controlled programmable attenuator, comprising:

a multi-tap resistive ladder network that attenuates an analog voltage signal to establish a plurality of voltage signals at its taps having different attenuation levels;

a plurality of voltage-to-voltage buffers that are connected between the respective taps and a common output, said buffers having respective digital inputs for receiving a digital signal that turns on one of said buffers so that the voltage signal at its tap is switched through to the common output while the other buffers are held off, each said buffer comprising,

wherein each buffer comprising an input stage that is always on such that it presents an approximately constant impedance at its tap, whether the buffer is on or off, so that a total impedance of the programmable attenuator, and thus a phase of the voltage signal switched through to the common output is approximately constant regardless of which buffer is switched on, and

an output stage that turns on and off in response to a digital signal at said digital input to selectively switch the voltage signal at the buffer'"'"'s tap through to the common output; and

a fixed gain stage that amplifies the voltage signal at the common output by a fixed gain level to set the attenuator'"'"'s overall gain range.

9. The digitally controlled programmable attenuator of claim 8, wherein said input stage conducts a bias current and comprises:

a current regulation circuit that reduces the bias current to reduce power consumption when the buffer is off.