High-impedance circuit having reduced stray capacitance
First Claim
1. A high-impedance circuit comprising:
- a differential pair circuit including a first transistor and a second transistor; and
a buffer circuit for converting an output of said differential pair circuit into a current so as to feedback a current to the differential pair circuit as an input current therefor;
whereinan output of the buffer circuit supplies respective base currents of said first transistor and said second transistor;
emitters of said first transistor and said second transistor are commonly connected to the ground via a first constant current source, and said differential pair circuit further comprises current determining means connected to said first transistor and said second transistor for determining currents which flow in said first transistor and said second transistor, respectively; and
said current determining means includes a first emitter resistance element inserted between the emitter of said first transistor and said first constant current source, and a second emitter resistance element inserted between the emitter of said second transistor and said first constant current source.
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Abstract
A high-impedance circuit includes a differential pair circuit composed of a first transistor and a second transistor, and a buffer circuit. The buffer circuit includes an NPN type transistor pair composed of a cascade connection of NPN type transistors and a PNP type transistor pair composed of a cascade connection of PNP type transistors, and bases of the NPN type transistors and bases of PNP type transistors respectively corresponding to the NPN type transistors are connected to each other, respectively so as to constitute current mirror circuits. An output of the differential pair circuit is connected to a cascade connection point of the NPN type transistor pair, and an emitter of an NPN type transistor included in the NPN type transistor pair is connected to the ground via a constant current source, and the emitter is connected to bases of the first transistor and the second transistor via resistors, respectively. Therefore, the output of the differential pair circuit is fed-back to inputs of the differential pair circuit, i.e. the bases of the first transistor and the second transistor as base currents.
20 Citations
22 Claims
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1. A high-impedance circuit comprising:
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a differential pair circuit including a first transistor and a second transistor; and a buffer circuit for converting an output of said differential pair circuit into a current so as to feedback a current to the differential pair circuit as an input current therefor;
whereinan output of the buffer circuit supplies respective base currents of said first transistor and said second transistor; emitters of said first transistor and said second transistor are commonly connected to the ground via a first constant current source, and said differential pair circuit further comprises current determining means connected to said first transistor and said second transistor for determining currents which flow in said first transistor and said second transistor, respectively; and said current determining means includes a first emitter resistance element inserted between the emitter of said first transistor and said first constant current source, and a second emitter resistance element inserted between the emitter of said second transistor and said first constant current source.
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2. A high-impedance circuit comprising:
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a differential pair circuit including a first transistor and a second transistor; and a buffer circuit for converting an output of said differential pair circuit into a current so as to feedback a current to the differential pair circuit as an input current therefor wherein; an output of the buffer circuit supplies respective base currents of said first transistor and said second transistor; emitters of said first transistor and said second transistor are commonly connected to the around via a first constant current source, and said differential pair circuit further comprises current determining means connected to said first transistor and said second transistor for determining currents which flow in said first transistor and said second transistor, respectively; and said current determining means includes base current determining means connected between the output of said buffer circuit and respective bases of said first transistor and said second transistor for determining respective base currents of said first transistor and said second transistor. - View Dependent Claims (3)
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4. A high-impedance circuit comprising:
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a differential pair circuit including a first transistor and a second transistor; and a buffer circuit for converting an output of said differential pair circuit into a current so as to feedback a current to the differential pair circuit as an input current therefor, wherein said buffer circuit includes a first cascade connection circuit including a first pair of transistors connected to each other in a cascade fashion and having a cascade connection point connected to the output of said differential pair circuit, and a base of one transistor of said first pair of transistors is connected to a signal terminal, and said buffer circuit further includes a second constant current source by which a constant current flows in said first cascade connection circuit, and a current according to the output of said differential pair circuit flows into or out of said first cascade connection circuit, and respective base currents of said first transistor and said second transistor are supplied in accordance with the current. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A high-impedance circuit, comprising:
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a differential pair circuit including a first transistor and a second transistor; base current compensating means including an input transistor to which a signal is inputted, and a cascade connection circuit and a current mirror connection circuit which compensate a base current of the input transistor; and an impedance dividing circuit connected between the differential pair circuit and the base current compensating means for dividing input impedance of the transistors of the differential pair circuit.
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18. A high-impedance circuit, comprising:
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a differential pair circuit including a first transistor and a second transistor; base current compensating means including an input transistor to which a signal is inputted, and a cascade connection circuit and a Darlington connection circuit which compensate a base current of the input transistor; and an impedance dividing circuit connected between the differential pair circuit and the base current compensating means for dividing input impedance of the transistors of the differential pair circuit.
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19. A high-impedance circuit, comprising:
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a differential pair circuit including a first transistor and a second transistor; current limiting means connected to the differential pair circuit for making currents of respective transistors of the differential pair circuit equal to each other; an input circuit including an input transistors to which a signal is inputted, and connected to one end of an output of the differential pair circuit and for compensating a base current of the input transistor and for feeding a difference between inputs of the differential pair circuit back to the differential pair circuit so as to balance the inputs of the differential pair circuit with each other;
whereinemitters of said first transistor and said second transistor are commonly connected to the around via a first constant current source, and said differential pair circuit further comprises current determining means connected to said first transistor and said second transistor for determining currents which flow in said first transistor and said second transistor, respectively; and a first emitter resistance element is inserted between the emitter of said first transistor and said first constant current source, and a second emitter resistance element is inserted between the emitter of said second transistor and said first constant current source.
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20. A television signal processing apparatus, comprising:
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a coupling capacitor for transferring a signal; and a high-impedance circuit connected to said coupling capacitor, said high-impedance circuit including a differential pair circuit which includes a first transistor and a second transistor, and a buffer circuit which includes a third transistor, and converts an output of one of the transistors of said differential pair circuit into a base current of said third transistor, and connects an output of said third transistor to another of the transistors of said differential pair circuit so as to feedback the output of said one of the transistors to said another of the transistors of said differential pair circuit, said buffer circuit including a first cascade connection circuit including a first pair of transistors connected to each other in a cascade fashion and having a cascade connection point connected to the output of said differential pair of circuit, and a base of one transistor of said first pair of transistors is connected to a signal terminal, said buffer circuit further including a constant current source by which a constant current flows in said first cascade connection circuit, and a current according to the output of said differential pair circuit flows into or out of said first cascade connection circuit, and respective base currents of said first transistor and said second transistor are supplied in accordance with the current. - View Dependent Claims (21)
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22. A high-impedance circuit, comprising:
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a differential pair circuit including a first transistor and a second transistor; and a buffer circuit including an input transistor having an input end connected to its base, wherein an output of one of said first transistor, and said second transistor of said differential pair circuit is inputted to said base of said input transistor after being converted by a factor of 1/(the current amplification factor of said input transistor)n where n is a positive integer, and an output of said input transistor is fed-back to the other of said first transistor and said second transistor of said differential pair circuit.
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Specification