Distributed write data drivers for burst access memories

• US 5,757,703 A
• Filed: 01/21/1997
• Issued: 05/26/1998
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy A., Merritt, Todd A.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/785,867
• Time in Patent Office: 490 Days
• Field of Search: 365/189.01, 365/189.05, 365/193, 365/233, 365/230.01, 365/202, 365/204
• US Class Current: 365/189.05
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near array sense amplifiers are used to control write data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

Claims

1. A memory device comprising:

a memory element array region;

a control circuit region;

a plurality of data line pairs dispersed throughout the memory element array region, each of the data line pairs comprising a true data line and a compliment data line;

a plurality of equilibration devices, each of the equilibration devices coupled to the true data line and the compliment data line of one of the plurality of data line pairs, and each of the equilibration devices responsive to an equilibrate signal from the control circuit region to couple the true data line to the compliment data;

a plurality of data sense amplifiers, each proximately located at least one of the data line pairs; and

a distributed plurality of write data drivers each comprising an equilibrate inactive input responsive to the equilibrate signal, a write active input responsive to a write enable signal from the control circuit region, a true write data output coupled to the true data line of one of the data line pairs and a compliment write data output coupled to the compliment data line of one of the data line pairs for driving data on the data line pairs in response to the equilibrate and write enable signals, each of the write data drivers proximately located to at least one of the data sense amplifiers.

2. The memory device of claim 1, further comprising:

a mode select circuit adapted to select between a mode of operation from at least EDO and Burst EDO modes, wherein the distributed plurality of write data drivers are each responsive to the mode.

3. A method of writing data into a memory device comprising steps of:

providing an address for the memory device;

asserting an equilibrate signal which is coupled to an equilibration device in order to equilibrate internal data lines of the memory device in response to the step of providing an address;

coupling the equilibrate signal to a plurality of data driver enable circuits;

coupling a write enable signal to the plurality of data driver enable circuits;

deasserting the equilibrate signal after the internal data lines are equilibrated;

gating the write enable signal through at least one of the data driver enable circuits in response to the step of deasserting the equilibrate signal;

driving data onto the internal data lines in response to the step of gating; and

storing data in a memory cell in response to the step of driving data.

4. The method of claim 3 wherein the step of providing an address is completed using an external microprocessor.

5. The method of claim 4 wherein the data is provided from the external microprocessor.