Semiconductor memory integrated circuit with simplified circuit structure
First Claim
1. A semiconductor memory device comprising:
- a first address register for storing an inputted address;
a second address register for storing a write address for a write data;
a comparing circuit for comparing the inputted address stored in said first address register and the write address stored in said second address register and for generating a control signal in accordance with the comparing result;
a memory cell array composed of a plurality of memory cells;
a write data register for storing the write data; and
a data output register for selectively receiving, as a selected data, one of the write data from said write data register and a read data from said memory cell array in response to the control signal and a register clock signal, and for outputting the selected data in response to the register clock signal.
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Accused Products
Abstract
In a semiconductor memory device, an first address register stores an inputted address and a second address register stores a write address for a write data. A comparing circuit compares both of the stored addresses, and generates a coincidence signal in accordance with the comparing result. A memory cell array composed of a plurality of memory cells. A write data register stores the write data. A data output register selectively receives, one of the write data from the write data register and a read data from the memory cell array as a selected data in response to the control signal and a register clock signal. Then, the data output register outputs the selected data in response to the register clock signal.
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Citations
20 Claims
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1. A semiconductor memory device comprising:
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a first address register for storing an inputted address; a second address register for storing a write address for a write data; a comparing circuit for comparing the inputted address stored in said first address register and the write address stored in said second address register and for generating a control signal in accordance with the comparing result; a memory cell array composed of a plurality of memory cells; a write data register for storing the write data; and a data output register for selectively receiving, as a selected data, one of the write data from said write data register and a read data from said memory cell array in response to the control signal and a register clock signal, and for outputting the selected data in response to the register clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of reading out a correct data in a semiconductor memory device, comprising the steps of:
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holding a write address; holding a write data; comparing an inputted read address and the write address to generate a selection control signal in an inactive level when the read address and the write address are not coincident with each other; reading a read data from a memory cell array in accordance with the read address; and selecting and outputting the read data in response to the selection control signal in the inactive level and a register clock signal. - View Dependent Claims (12, 13, 14, 15)
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16. A semiconductor memory device, comprising:
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a memory cell array composed of a plurality of memory cells, for storing a read data;
first holding means for holding a write address;second holding means for holding a write data; comparing means for comparing an inputted read address and the write address to generate a selection control signal in an inactive level when the read address and the write address are not coincident with each other; read means for reading the read data from said memory cell array in accordance with the read address; and data output means for selecting and outputting the read data in response to the selection control signal in the inactive level and a register clock signal. - View Dependent Claims (17, 18, 19, 20)
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Specification