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Semiconductor memory integrated circuit with simplified circuit structure

  • US 5,757,704 A
  • Filed: 06/23/1997
  • Issued: 05/26/1998
  • Est. Priority Date: 07/30/1996
  • Status: Expired due to Fees
First Claim
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1. A semiconductor memory device comprising:

  • a first address register for storing an inputted address;

    a second address register for storing a write address for a write data;

    a comparing circuit for comparing the inputted address stored in said first address register and the write address stored in said second address register and for generating a control signal in accordance with the comparing result;

    a memory cell array composed of a plurality of memory cells;

    a write data register for storing the write data; and

    a data output register for selectively receiving, as a selected data, one of the write data from said write data register and a read data from said memory cell array in response to the control signal and a register clock signal, and for outputting the selected data in response to the register clock signal.

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