High speed self-adjusting clock recovery circuit with frequency detection

• US 5,757,857 A
• Filed: 03/13/1996
• Issued: 05/26/1998
• Est. Priority Date: 07/21/1994
• Status: Expired due to Fees

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Buchwald, Aaron W.
• Primary Examiner(s): VO, DON NGUYEN
• Application Number:
  US08/392,958
• Time in Patent Office: 804 Days
• Field of Search: 375/261, 375/271, 375/279, 375/322, 375/324, 375/326, 375/327, 375/329, 375/344, 375/343, 375/354, 375/371, 329/304, 329/306, 329/307, 329/345, 329/346
• US Class Current: 375/271
• CPC Class Codes: H04L 7/0274 with Costas loop

Abstract

A clock recovery circuit based upon an early-late gate approach is applied to high speed serial communication links using NRZ data. The circuit has no systematic phase offset and therefore requires no external phase adjustment circuits or mechanisms. The circuit is used in high speed integrated receivers for applications including fiber optics, disk-drive read/write electronics, mobile communications and high rate- twisted pair data transmission in multimedia systems. Quadrature samples are obtained and held which follow the shape of the NRZ data transition as a function of phase offset. The data signal is passed through the limiter giving rise to a sawtooth shaped phase error signal. A derivative of the error function is taken to provide a frequency error signal to provide for frequency detection and assistance in frequency acquisition of the phase lock loop circuit generating the recovered clock signal from a variably controlled oscillator.

Claims

1. A clock recovery circuit for establishing bit synchronization with an NRZ data formatted bit stream comprising:

a matched filter for receiving said NRZ data formatted bit stream for producing a filtered output signal indicative of edge transitions in said NRZ data formatted bit stream;

first and second sample and hold circuits having inputs coupled to said matched filter, said sample and hold circuits being complementarily clocked by a VCO signal to hold quadrature samples, said first sample and hold circuit for generating an in-phase data output signal;

a third sample and hold circuit having an input coupled to said second sample and hold circuit, said third sample and hold circuit being clocked on positive and negative transitions of said in-phase data output signal and generating a data crossover sample;

a multiplier for multiplying said in-phase data output signal with output from said third sample and hold circuit;

a lowpass filter coupled to said multiplier for filtering output of said multiplier to generate a DC value of a phase error signal proportional to any phase error between said in-phase data output signal and said data crossover sample; and

a variable controlled oscillator (VCO) having its control input coupled to said low ass filter, said variable controlled oscillator generating said VCO signal with a controllable phase according to said DC value provided by said lowpass filter, said VCO being coupled to said first and second sample and hold circuits to complementarily clock said first and second sample and hold circuits,

whereby a data transition tracking loop is provided which is high speed, inherently self-adjusting;

is independent of data transition density with significantly reduced ripple in said phase error signal generated by said multiplier.

2. The circuit of claim 1 further comprising a first limiter coupled to the output of said first sample and hold circuit, said first limiter having an output coupled to said multiplier so that output of said multiplier representative of said phase error is monotonic across said phase error signal centered on a bit interval, said output of said limiter being said in-phase data output signal.

3. The circuit of claim 2 wherein said phase error signal output by said multiplier is a sawtooth wave form.

4. The circuit of claim 1 further comprising a limiter coupled to said VCO signal of said VCO for generating a clock signal indicative of a recaptured clock from said NRZ data formatted bit stream.

5. The circuit of claim 2 further comprising a second limiter coupled to said VCO signal of said VCO for generating a clock signal indicative of a recaptured clock from said NRZ data formatted bit stream.

6. The circuit of claim 2 further comprising a frequency lock detector for providing a frequency error signal to said VCO, said VCO being responsive to said frequency error signal to shift frequency of said VCO in alignment with bit rate frequency of said NRA data formatted bit stream prior to phase lock.

7. The circuit of claim 6 wherein said frequency lock detector is enabled only when absolute value of phase error exceeds a predetermined threshold.

8. The circuit of claim 3 further comprising a frequency lock detector for providing a frequency error signal to said VCO, said VCO being responsive to said frequency error signal to shift frequency of said VCO in alignment with bit rate frequency of said NRZ data formatted bit stream prior to phase lock.

9. The circuit of claim 1 arranged and configured to operate in a bit interleaved fashion so that said first and second sample and hold circuits each constitute a pair of complementarily clocked tracking and hold circuits having their input coupled to said matched filter and a multiplexer having its inputs coupled to outputs of said pair of tracking and hold circuits, said tracking and hold circuits being complementarily clocked by selected outputs from said VCO, said VCO having a lead output, Q, and an lag output, I, said tracking and hold circuits of said first sample and hold circuit being clocked by said lag output from said VCO while said pair of tracking and hold circuits of said second sample and hold circuit are clocked by said lead output from said VCO.

10. The circuit of claim 9 wherein said third sample and hold circuit constitutes:

a pair of complementarily clocked tracking and hold circuits complementarily clocked by said in-phase data output signal and having their input coupled to an output of said multiplexer included within said second sample and hold circuit which generates data cross-over samples;

a multiplexer coupled to outputs from said pair of tracking and hold circuits included in said third sample and hold circuit, said multiplexer of said third sample and hold circuit having an output coupled to said lowpass filter; and

an inverter coupled between an output of one of said tracking and hold circuits and an input of said multiplexer to invert tracked and held data crossover samples when said tracking and hold circuit coupled thereto is clocked by a negative transition of said data output signal.

11. The circuit of claim 10 wherein said tracking and hold circuits and multiplexers comprising said first, second and third sample and hold circuits are matched through substantially identical integrated circuit fabrication to inherently null out systematic phase errors within each of said sample and hold circuits.

12. The circuit of claim 11 further comprising a frequency lock detector for providing a frequency error signal to said VCO, said VCO being responsive to said frequency error signal to shift frequency of said VCO in alignment with bit rate frequency of said NRZ data formatted bit stream prior to phase lock.

13. The circuit of claim 12 wherein said frequency lock detector comprises a fourth sample and hold circuit comprised of:

a pair of tracking and hold circuits complementarily clocked by said inphase data output signal each having their inputs coupled to said lowpass filter;

a multiplexer having its inputs coupled to outputs of said pair of tracking and hold circuits of said fourth sample and hold circuit;

a second lowpass filter having its input coupled to an output of said multiplexer of said fourth sample and hold circuit;

a summing node coupled to said second lowpass filter for differencing with said phase error signal; and

a limiter having its input coupled to said summing node to generate a frequency error signal.

14. The circuit of claim 13 further comprising a lock detect gate for breaking connection between said limiter and said lowpass filter when absolute value of said phase error signal is below a predetermined threshold, so that said VCO is controlled only by said phase error below said threshold and by said frequency error above said threshold.

15. A method of recovering a clock signal from an NRZ data bit stream comprising the steps of:

detecting edge transitions of said NRZ data bit stream;

generating a quadrature sample signal corresponding to said NRZ data bit stream;

selectively passing said quadrature sample signal to a phase detector output, said quadrature sample signal being passed to said phase detector output if said NRZ data makes a low to high transition, a negative of said quadrature sample signal being passed to said phase detector output if said NRZ data signal makes a high to low transition, otherwise if said NRZ data signal makes no transition, holding a previous phase error value in said phase detector output;

controlling a variably controlled oscillator (VCO) according to said phase detector output; and

generating a recaptured clock signal by said controlled VCO, whereby said clock signal is recovered in a self-adjusting circuit with no steady state phase error, whereby ripple induced phase jitter is substantially eliminated, whereby phase error output is independent of data density and high speed operation is enabled.

16. The method of claim 15 further comprising the step of generating from said output of said phase error detector a frequency error signal, said frequency error signal being selectively combined with output of said phase detector to control frequency of said VCO to thereby frequency lock to said NRZ data bit stream.

17. The method of claim 15 further comprising the step of generating a monotonically increasing phase error signal extending across a bit interval centered on zero phase error for controlling said VCO.

18. The method of claim 17 wherein the step of generating said monotonically increasing phase error signal generates a sawtooth wave form.

19. The method of claim 18 wherein said frequency error signal is generated from said sawtooth wave form and further comprising the step of generating from said output of said phase error detector a frequency error signal, said frequency error signal being selectively combined with output of said phase detector to control frequency of said VCO to thereby frequency lock to said NRZ data bit stream.

20. A circuit for recapturing a clock signal from an NRZ data bit stream comprising:

clocked sample and hold circuit means for sampling and holding an in-phase sample signal of said NRZ data bit stream;

clocked sample and hold circuit means for sampling and holding-a quadrature sample signal of said NRZ data bit stream;

phase detector circuit means for selectively passing said quadrature sample signal to a phase detector output, said quadrature sample signal being passed to said phase detector output if said NRZ data makes a low to high transition, the negative of said quadrature sample signal being passed to said phase detector output if said NRZ data makes a high to low transition, and previously passed quadrature sample signal being held at said phase detector output if said NRZ data makes no transition; and

variable controlled oscillator means for receiving said phase detector output and responsively generating an in-phase clock signal, said clocked sample and hold circuit means for sampling and holding an in-phase sample signal of said NRZ data bit stream and said clocked sample and hold circuit means for sampling and holding a quadrature sample signal of said NRZ data bit stream being complementarily clocked by said inphase clock signal.