Apparatus and method for initializing a master/checker fault detecting microprocessor

• US 5,758,058 A
• Filed: 02/27/1996
• Issued: 05/26/1998
• Est. Priority Date: 03/31/1993
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Milburn, Blair D.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): VALES, PHILLIP
• Application Number:
  US08/607,523
• Time in Patent Office: 819 Days
• Field of Search: 395/182.08, 395/182.09, 395/700, 371/68.1, 371/67.1
• US Class Current: 714/11
• CPC Class Codes: G06F 11/1637 using additional compare functionality in one or some but not all of the redundant processing components
• CPC Class Codes: G06F 11/1654 where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O
• CPC Class Codes: G06F 11/1675 Temporal synchronisation or re-synchronisation of redundant processing components

Abstract

A method and apparatus for initializing both processors in a master/checker fault detecting microprocessor. A microcode initialization routine is run by each processor upon reset of both of the processors in the pair. The routines cause each processor to be initialized, such that the two processors complete initialization at the same time and operate in a lock-step manner.

Claims

1. A method for initializing a first device and a second device coupled in a master/checker fault detecting arrangement, the method comprising the steps of:

asserting a reset signal to the first device and the second device at the same time;

designating both the first device and the second device as checkers;

signaling identical initialization microcode routines in both the first device and the second device;

the first device and the second device simultaneously and independently executing a first initialization microcode routine and a second initialization microcode routine respectively in response to the step of signaling, and further wherein each initialization microcode routine includes the steps of

initializing internal state of its device to a known value, and

determining whether the device is to be either a master or a checker,

internally setting the device to be either a master or a checker based on determining whether the device is to be a master or checker,

wherein the first microcode routine and the second microcode routine are completed at the same time, such that the first device and the second device complete initialization at the same time, thereby initializing the first device and the second device to operate in lock-step.

2. The method as defined in claim 1 wherein the step of determining further comprises the steps of:

reading at least one control signal from a memory storage element; and

internally setting either the first or second device as a master or a checker according to said at least one control signal.

3. The method as defined in claim 2 wherein the step of reading comprises the steps of the first device reading a first control bit from a first memory storage element and the second device reading a second control bit from a second memory storage element, and setting either the first device or the second device to be the master if the first control bit or the second control bit respectively to a first logic state;

and setting either the first device or the second device to be a checker if the first control bit or the second control bit respectively is set to a second logic.

4. The method as defined in claim 3 wherein the control bit for the first device and the second control for the second device are read from their respective in-circuit emulation (ICE) buses.

9. The method as defined in claim 1 further comprising the steps of each initialization microcode routine initializing outputs of a scan-out mechanism to known, deterministic states.

5. A method for initializing a first device and a second device coupled in a master/checker fault detecting arrangement, the method comprising the steps of:

asserting a reset signal to the first device and the second device at the same time;

designating the first device and the second device as checkers;

de-asserting the reset signal;

signaling identical initialization microcode routines in both the first device and the second device;

the first device and the second device executing simultaneously and independently, a first initialization microcode routine and a second initialization microcode routine respectively in response to the step of signaling, and further wherein each initialization microcode routine includes the steps of

initializing internal state of its device to a known value,

reading control information from a memory storage element, and

internally setting the device as a master or a checker according to said control information;

completing the first initialization microcode routine and the second initialization microcode routine at the same time, such that the first device and the second device complete initialization at the same time, thereby initializing the first device and the second device to operate in lock-step.

6. The method as defined in claim 5 wherein the step of reading comprises the steps of the first device reading a first control bit from a first memory storage element and the second device reading a second control bit from a second memory storage element, and setting either the first device or the second device to be the master if the first control bit or the second control bit respectively is set to a first logic state;

and setting either the first device or the second device is set to be a checker if the first control bit or the second control bit respectively is set to a second logic state.

7. The method as defined in claim 6 wherein the first control bit for the first device and the second control bit for the second device are read from their respective in-circuit emulation (ICE) buses.

10. The method as defined in claim 5 further comprising the steps of each initialization microcode routine initializing outputs of a scan-out mechanism to known, deterministic states.

8. A fault detecting microprocessor for use in a computer system comprising:

a first processor having a plurality of inputs and a plurality of outputs; and

a second processor coupled to said first processor in a master/checker arrangement and

wherein the first processor and the second processor include a first microcode unit and a second microcode unit respectively, and further wherein the first processor and the second processor are designated as checkers in response to assertion of a reset signal and the first and second microcode units are signaled to begin executing first and second initialization microcode routines respectively at the same time after deassertion of the reset signal, wherein the first and second initialization microcode routines are identical and are executed simultaneously and independently of each other, and further wherein the first and second initialization microcode routines set internal states of the first and second processors respectively for initialization to known values and cause the first and second processors to be set as either as a master or a checker according to at least one control signal, wherein the first processor and the second processor complete initialization at the same time to operate in lock-step.

11. The method as defined in claim 8 wherein each of first and second processors comprises a scan-out mechanism and further wherein each initialization microcode routine initializing outputs of a scan-out mechanism to known, deterministic states.