Apparatus and method for initializing a master/checker fault detecting microprocessor
First Claim
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1. A method for initializing a first device and a second device coupled in a master/checker fault detecting arrangement, the method comprising the steps of:
- asserting a reset signal to the first device and the second device at the same time;
designating both the first device and the second device as checkers;
signaling identical initialization microcode routines in both the first device and the second device;
the first device and the second device simultaneously and independently executing a first initialization microcode routine and a second initialization microcode routine respectively in response to the step of signaling, and further wherein each initialization microcode routine includes the steps ofinitializing internal state of its device to a known value, anddetermining whether the device is to be either a master or a checker,internally setting the device to be either a master or a checker based on determining whether the device is to be a master or checker,wherein the first microcode routine and the second microcode routine are completed at the same time, such that the first device and the second device complete initialization at the same time, thereby initializing the first device and the second device to operate in lock-step.
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Abstract
A method and apparatus for initializing both processors in a master/checker fault detecting microprocessor. A microcode initialization routine is run by each processor upon reset of both of the processors in the pair. The routines cause each processor to be initialized, such that the two processors complete initialization at the same time and operate in a lock-step manner.
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Citations
11 Claims
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1. A method for initializing a first device and a second device coupled in a master/checker fault detecting arrangement, the method comprising the steps of:
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asserting a reset signal to the first device and the second device at the same time; designating both the first device and the second device as checkers; signaling identical initialization microcode routines in both the first device and the second device; the first device and the second device simultaneously and independently executing a first initialization microcode routine and a second initialization microcode routine respectively in response to the step of signaling, and further wherein each initialization microcode routine includes the steps of initializing internal state of its device to a known value, and determining whether the device is to be either a master or a checker, internally setting the device to be either a master or a checker based on determining whether the device is to be a master or checker, wherein the first microcode routine and the second microcode routine are completed at the same time, such that the first device and the second device complete initialization at the same time, thereby initializing the first device and the second device to operate in lock-step. - View Dependent Claims (2, 3, 4, 9)
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5. A method for initializing a first device and a second device coupled in a master/checker fault detecting arrangement, the method comprising the steps of:
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asserting a reset signal to the first device and the second device at the same time; designating the first device and the second device as checkers; de-asserting the reset signal; signaling identical initialization microcode routines in both the first device and the second device; the first device and the second device executing simultaneously and independently, a first initialization microcode routine and a second initialization microcode routine respectively in response to the step of signaling, and further wherein each initialization microcode routine includes the steps of initializing internal state of its device to a known value, reading control information from a memory storage element, and internally setting the device as a master or a checker according to said control information; completing the first initialization microcode routine and the second initialization microcode routine at the same time, such that the first device and the second device complete initialization at the same time, thereby initializing the first device and the second device to operate in lock-step. - View Dependent Claims (6, 7, 10)
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8. A fault detecting microprocessor for use in a computer system comprising:
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a first processor having a plurality of inputs and a plurality of outputs; and a second processor coupled to said first processor in a master/checker arrangement and wherein the first processor and the second processor include a first microcode unit and a second microcode unit respectively, and further wherein the first processor and the second processor are designated as checkers in response to assertion of a reset signal and the first and second microcode units are signaled to begin executing first and second initialization microcode routines respectively at the same time after deassertion of the reset signal, wherein the first and second initialization microcode routines are identical and are executed simultaneously and independently of each other, and further wherein the first and second initialization microcode routines set internal states of the first and second processors respectively for initialization to known values and cause the first and second processors to be set as either as a master or a checker according to at least one control signal, wherein the first processor and the second processor complete initialization at the same time to operate in lock-step. - View Dependent Claims (11)
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Specification