Multimedia communication apparatus and methods

• US 5,758,075 A
• Filed: 09/24/1996
• Issued: 05/26/1998
• Est. Priority Date: 07/29/1994
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Graziano, Michael J., Stanley, Daniel L., Hauris, Jon F.
• Primary Examiner(s): DINH, DUNG C
• Application Number:
  US08/719,050
• Time in Patent Office: 609 Days
• Field of Search: 395/200.8, 395/200.81, 395/200.61, 395/874, 395/875, 395/876, 395/872, 370/438, 370/439, 370/463
• US Class Current: 709/250
• CPC Class Codes: G06F 13/128 for dedicated transfers to a network for protocol converters G06F13/387
• CPC Class Codes: H04L 12/433 with asynchronous transmission, e.g. token ring, register insertion
• CPC Class Codes: H04L 12/6418 Hybrid transport
• CPC Class Codes: H04L 2012/6435 Bus
• CPC Class Codes: H04L 2012/6448 Medium Access Control [MAC]
• CPC Class Codes: H04L 2012/6489 Buffer Management, Threshold setting, Scheduling, Shaping
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9031 Wraparound memory, e.g. overrun or underrun detection
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9063 Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9089 replacing packets in a storage arrangement, e.g. pushout
• CPC Class Codes: H04L 63/0428 wherein the data content is protected, e.g. by encrypting or encapsulating the payload
• CPC Class Codes: H04L 63/083 using passwords cryptographic mechanisms or cryptographic arrangements for entity authentication using a predetermined code H04L9/3226
• CPC Class Codes: H04L 65/1101 Session protocols
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A communications adapter receives and transmits simultaneously packet and/or isochronous data between two interfaces; a network and a host bus system. The adapter stores the isochronous and packet data in receive and transmit queues configured in a FDDI RAM buffer. A controller manages the transfers of the data into and out of the queues. A local bus interacts with the system to provide descriptors of addresses in the system for transfers of data out of the queues to the system or the network. The controller is programmable to provide a variable threshold for the transfer of data between the queues and the system or the network. A systems interface unit handles the transfer of data to/from the system and allows data to bypass the queues and directly access the system or the network.

Claims

1. A method of controlling the delivery of data from an adapter including a controller, storage queues, a local processor and a local processor bus to a host bus system using a receive engine, comprising the steps of:

a) storing data in the queues;

b) issuing a request by the receive engine to the system for data delivery;

c) issuing a request by the receive engine to the local bus interface for (i) data delivery and (ii) a descriptor list of addresses in the system for the storage of data;

d) assigning a temporary storage buffer to a filled queue by the receive engine;

e) filling the temporary storage buffer with data from the queues by the controller on signal from the receive engine; and

f) signalling the system by the receive engine to empty the temporary storage buffer to the system at addresses specified in the descriptor list.

2. The method of claim 1 further comprising the steps of:

a) polling an internal status register of the controller to determine whether a queue is ready to be emptied; and

b) initiating the request for data delivery when the status register indicates the queue is filled.

3. The method of claim 2 further comprising the steps of:

a) forming descriptor pointers for each queue which locate a chain of linked descriptors in a local bus memory.

4. The method of claim 3 further comprising the steps of:

a) forming a received descriptor which is initialized by the local processor and a local bus memory to indicate to the receive engine the destination for received data.

5. The method of claim 4 further comprising the step of:

a) providing for each received descriptor a control word, a byte count, an address low, an address high and a linked pointer.

6. The method of claim 5 further comprising the step of:

a) transferring data through the receive engine to a destination in the system till either the byte count field is exhausted or an end of frame has been reached.

7. The method of claim 6 further comprising the step of:

a) transferring the receive engine to the next descriptor in the list and continuing the transfer of data to the system.

8. The method of claim 7 further comprising the step of:

a) updating the control word and byte count and moving to the next descriptor in the list when an end of frame is reached.

9. The method of claim 8 further comprising the steps of:

a) forming a plurality of FIFO registers in the temporary storage buffer;

b) filling the FIFO with data from a designated queue; and

c) unloading the FIFO once it becomes half-full using a host bus system interface or local processor bus interface.

10. The method of claim 9 further comprising the steps of:

a) terminating the transfer of data to the host system bus interface or the local processor bus interface when the FIFO becomes full; and

b) reinitiating the transfer of data when at least a selected number of bytes are available in the FIFO.

11. A method of controlling the delivery of data to an adapter including a controller, storage queues, a local processor and a local processor bus from a host bus system using a transmit engine, comprising the steps of:

a) issuing a request to a local bus interface by the transmit engine to fetch a descriptor list for the transfer of data from the system;

b) assigning a queue to a temporary storge buffer in the transmit engine;

c) issuing a request to the system or the local bus by the transmit engine to begin filling the temporary storage buffer;

d) issuing a request to the controller by the transmit engine to begin unloading the temporary storage buffer and filling the storage queues;

e) signalling the transmit engine by the controller when the queue is almost full; and

f) signalling the system or the local bus by the transmit engine to stop filling the temporary storage buffer.

12. The method of claim 11 further comprising the step of:

a) issuing a request to a slave transport port by a data device coupled to the system to write directly to a queue;

b) issuing a request to the controller by the slave transmit port for assignement of a storage queue to store system data;

c) loading a storage buffer in the slave transmit port by the system; and

d) emptying the storage buffer by the controller to a queue indicated by a system address.

13. The method of claim 12 further comprising the step of:

a) assigning the FIFO to another queue after the FIFO has been unloaded by the controller.

14. The method of claim 11 further comprising the step of:

a) forming a transmit descriptor containing a control word, a byte count, an address low, an address high, and a linked pointer.

15. The method of claim 14 further comprising the steps of:

a) forming descriptor pointers that locate a chain of linked transmit descriptors in a local bus memory; and

b) accessing a descriptor in the list using a transmit descriptor pointer in a base field of a local processor bus address register, the least significant bit of the transmit descriptor pointer being a Queue Enable Bit (QEN).

16. The method of claim 15 further comprising the step of

a) processing each descriptor by loading the linked pointer field into the transmit descriptor pointer and fetching the next descriptor in the chain until a linked pointer of zero is encountered.

17. The method of claim 16 further comprising the step of:

a) disenabling the QEN bit of the transmit descriptor pointer when the linked pointer is zero.

18. The method of claim 17 further comprising the steps of:

a) receiving a signal from a controller wherein a queue is ready for data;

b) fetching a valid descriptor for the queue; and

c) assigning a queue to a FIFO register in the temporary storage buffer.

19. A method of controlling the delivery of data from a host bus system using a slave transmit engine to an adapter including a controller, storage queues, a local processor, a local processor bus and a local memory comprising the steps:

a) assigning a queue to a temporary storage buffer contained in the slave transmit engine;

b) using the system interface unit to load the temporary storage buffer with data from the host bus system;

c) using the controller to transfer data from the temporary storage buffer to the queue indicated by a system address; and

d) transferring the data to the queue using a streaming data or basic transfer mode.

20. The method of claim 19 wherein a shared memory buffer allows input/output devices on the system to read and write local bus memory and accesses to the shared memory buffer cause the system interface unit to become bus master of the local bus in transferring data therebetween.

21. The method of claim 20 further comprising the step of:

buffering the transferred data in the shared memory buffer.

22. Apparatus for controlling the delivery of data from an adapter including a controller, storage queues, a local processor and a local processor bus to a host bus system using a receive engine, comprising:

a) means for storing data in the queues;

b) means for issuing a request by the receive engine to the system for data delivery;

c) means for issuing a request by the receive engine to a local bus interface for (i) data delivery and (ii) a descriptor list of addresses in the system for the storage of data;

d) means for assigning a temporary storage buffer to a filled queue by the receive engine;

e) means for filling the temporary storage buffer with data from the queues by the controller on signal from the receive engine; and

f) means for signalling the system by the receive engine to empty the buffer to the system at addresses specified in the descriptor list.

23. The apparatus of claim 22 further comprising:

a) means for polling an internal status register of the controller to determine whether a queue is ready to be emptied; and

b) means for initiating the request for data delivery when the status register indicates the queue is filled.

24. The apparatus of claim 23 further comprising:

a) means for forming descriptor pointers for each queue which locate a chain of linked descriptors in a local bus memory.

25. The apparatus of claim 24 further comprising:

a) means for forming a received descriptor which is initialized by the local processor and a local bus memory to indicate to the receive engine the destination for received data.

26. The apparatus of claim 25 further comprising:

a) means for providing for each received descriptor a control word, a byte count, an address low, an address high and a linked pointer.

27. The apparatus of claim 26 further comprising:

means for transferring data through the receive engine to a destination in the system till either the byte count field is exhausted or an end of frame has been reached.

28. The apparatus of claim 27 further comprising:

means for transferring the receive engine to the next descriptor in the list and continuing the transfer of data to the system.

29. The apparatus of claim 28 further comprising:

means for updating the control word and byte count and moving to the next descriptor in the list when an end of frame is reached.

30. The apparatus of claim 29 further comprising:

a) means for forming a plurality of FIFO registers in the temporary storage buffer;

b) means for filling the FIFO with data from a designated queue; and

c) means for unloading the FIFO once it becomes half-full using a host bus system interface or local processor bus interface.

31. The apparatus of claim 30 further comprising:

a) means for terminating the transfer of data to the host system bus interface or the local processor bus interface when the FIFO becomes full; and

b) means for reinitiating the transfer of data when at least a selected number of bytes are available in the FIFO.

32. Apparatus for controlling the delivery of data from a host bus system using a transmit engine to an adapter including a controller, storage queues, a local processor and a local processor bus, comprising:

a) means for issuing a request to a local bus interface by the transmit engine to fetch a descriptor list for the transfer of data from the system;

b) means for assigning a queue to a temporary storage buffer in the transmit engine;

c) means for issuing a request to the system or the local bus by the transmit engine to begin filling the temporary storage buffer;

d) means for issuing a request to the controller by the transmit engine to begin unloading the temporary storage buffer and filling the storage queues;

e) means for signalling the transmit engine by the controller when the queue is almost full; and

f) means for signalling the system or the local bus by the transmit engine to stop filling the temporary storage buffer.

33. The apparatus of claim 32 further comprising:

means for forming a transmit descriptor containing a control word, a byte count, an address low, an address high, and a link pointer.

34. The apparatus of claim 33 further comprising:

a) means for forming descriptor pointers that locate a chain of link transmit descriptors in a local bus memory; and

b) means for accessing a descriptor in the list using a transmit descriptor pointer in a base field of a local processor bus address register, the least significant bit of the transmit descriptor pointer being a Queue Enable Bit (QEN).

35. The apparatus of claim 34 further comprising:

means for processing each descriptor by loading the linked pointer field into the transmit descriptor pointer and fetching the next descriptor in the chain until a linked pointer of zero is encountered.

36. The apparatus of claim 35 further comprising:

means for disenabling the QEN bit of the transmit descriptor pointer when the linked pointer is zero.

37. The apparatus of claim 36 further comprising:

a) means for receiving a signal from a controller wherein a queue is ready for data;

b) means for fetching a valid descriptor for the queue;

c) means for assigning a queue to a FIFO register in the temporary storage buffer.

38. The apparatus of claim 37 further comprising:

a) means for issuing a request to a slave transport port by a data device coupled to the system to write directly to a queue;

b) means for issuing a request to the controller by the slave transmit port for assignment of a storage queue to store system data;

c) means for loading a storage buffer in the slave transmit port by the system; and

d) means for emptying the storage buffer by the controller to a queue indicated by a system address.

39. The apparatus of claim 38 further comprising:

means for assigning the FIFO to another queue after the FIFO has been unloaded by the controller.

40. The apparatus of claim 39 further comprising:

a) means for controlling the delivery of data to an adapter including a controller, storage queues, a local processor, a local processor bus and a local memory from a host bus system using a slave transmit engine;

b) means for assigning a queue to a temporary storage buffer contained in the slave transmit engine;

c) means for using the system interface unit to load the temporary storage buffer with data from the host bus system;

d) means for using the controller to transfer data from the FIFO to the queue indicated by a system address; and

e) means for transferring the data to the queue using a streaming data or basic transfer mode.

41. Apparatus for controlling the delivery of data from an adapter including a controller, storage queues, a local processor and a local processor bus to a host bus system comprising:

a) means for issuing a request to a slave transport port by a data device coupled to the system to write directly to a queue;

b) means for issuing a request to the controller by the slave transmit port for assignment of a storage queue to store system data;

c) means for loading a storage buffer in the slave transmit port by the system; and

d) means for emptying the storage buffer by the controller to a queue indicated by a system address.

42. The apparatus of claim 41 further comprising means for assigning the FIFO to another queue after the FIFO has been unloaded by the controller.

43. Apparatus controlling the delivery of data from a host bus system using a slave transmit engine to an adapter including a controller, storage queues, a local processor, a local processor bus and a local memory comprising:

a) means for assigning a queue to a temporary storage buffer contained in the slave transmit engine;

b) means for using the system interface unit to load the temporary storage buffer with data from the host bus system;

c) means for using the controller to transfer data from the temporary storage buffer to the queue indicated by a system address; and

d) means for transferring the data to the queue using a streaming data or basic transfer mode.

44. The apparatus of claim 43 further comprising a shared memory buffer which allows input/output devices on the system to read and write local bus memory and accesses to the shared memory buffer which cause the system interface unit to become bus master of the local in transferring data therebetween.

45. The apparatus of claim 44 further comprising means for buffering the transferred data in the shared memory buffer.

46. An article of manufacturing comprising:

a computer usable medium having computer readable program code means embodied therein for controlling the delivery of data from an adapter including a controller, storage queues, a local processor and a local processor bus to a host bus system using a receive engine, the computer readable program code means in said article of manufacturing comprising;

a) computer readable program code means for storing data in the queues;

b) computer readable program code means for issuing a request by the receive engine to the system for data delivery;

c) computer readable program code means for issuing a request by the receive engine to a local bus interface for (i) data delivery and (ii) a descriptor list of addresses in the system for the storage of data;

d) computer readable code means for assigning a temporary storage buffer to a filled queue by the receive engine;

e) computer readable code means for filling the temporary storage buffer with data from the queues by the controller on signal from the receive engine; and

f) computer readable code means for signalling the system by the receive engine to empty the buffer to the system at addresses specified in the descriptor list.

47. An article of manufacture, comprising:

a computer usable medium having computer readable program code means embodied therein for controlling the delivery of data from a host bus system using a transmit engine to an adapter including a controller, storage queues, a local processor and a local processor bus, the computer readable program code means in said article of manufacture comprising;

a) computer readable program code means for issuing a request to a local bus interface by the transmit engine to fetch a descriptor list for the transfer of data from the system;

b) computer readable program code means for assigning a queue to a temporary storage buffer in the transmit engine;

c) computer readable program code means for issuing a request to the system or the local bus by the transmit engine to begin filling the temporary storage buffer;

d) computer readable program code means for issuing a request to the controller by the transmit engine to begin unloading the temporary storage buffer and filling the storage queues;

e) computer readable program code means for signalling the transmit engine by the controller when the queue is almost full; and

f) computer readable program code means for signalling the system or the local bus by the transmit engine to stop filling the temporary storage buffer.

48. An article of manufacture, comprising:

a computer usable medium having computer readable program code means embodied therein for controlling the delivery of data from a host bus system using a slave transmit engine to an adapter including a controller, storage queues, a local processor, a local processor bus and a local memory, the computer readable program code means in said article of manufacture comprising;

a) computer readable program code means for assigning a queue to a temporary storage buffer contained in the slave transmit engine;

b) computer readable program code means for using a system interface unit to load the temporary storage buffer with data from the host bus system;

c) computer readable program code means for using the controller to transfer data from the temporary storage buffer to the queue indicated by a system address; and

d) computer readable program code means for transferring the data to the queue using a streaming data or basic transfer mode.