Process for fabricating a solder bump for a flip chip integrated circuit

• US 5,759,910 A
• Filed: 12/23/1996
• Issued: 06/02/1998
• Est. Priority Date: 12/23/1996
• Status: Expired due to Term

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lance, James George Jr., Mangold, Rick Lee
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/773,248
• Time in Patent Office: 526 Days
• Field of Search: 437/183, 437/188, 437/189, 437/192, 437/203, 438/612, 438/613, 438/614, 438/615
• US Class Current: 438/613
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A process for fabricating a solder bump having an improved geometry includes the steps of evaporatively depositing a first metallization system to form a post having a predetermined volume onto an integrated circuit having a passivation layer defining a die pad window, wherein the length of the post is greater than the width of the post, and wherein the length of the post extends beyond the die pad window over the passivation layer, and evaporatively depositing a second metallization system onto the post to form a cap also having a volume, wherein the first metallization system forming the post and the second metallization system forming the cap, when reflowed, form a eutectic solder bump.

Claims

1. A process for fabricating a solder bump having an improved geometry comprising the steps of:

evaporatively depositing a first metallization system to form a post having a predetermined volume onto an integrated circuit having a passivation layer defining a die pad window, wherein the length of the post is greater than the width of the post and wherein the length of the post extends beyond the die pad window over the passivation layer; and

evaporatively depositing a second metallization system onto the post to form a cap also having a volume,

wherein the first metallization system forming the post and the second metallization system forming the cap, when reflowed, form a eutectic solder bump.

2. The process for fabricating a solder bump according to claim 1, wherein the first metallization system forming the post is lead.

3. The process for fabricating a solder bump according to claim 1, wherein the second metallization system forming the cap is tin.

4. The process for fabricating a solder bump according to claim 1, wherein the post has a major axis extending substantially parallel to the length of the post and substantially normal to the edge of the integrated circuit die.

5. The process for fabricating a solder bump according to claim 1, wherein the predetermined volume of the post and the volume of the cap provide a volume of eutectic tin-lead solder.

6. The process for fabricating a solder bump according to claim 1, wherein the post and cap are evaporatively deposited in two substantially parallel, staggered rows of solder bumps having the improved geometry.

7. The process for fabricating a solder bump according to claim 1, wherein the length of the post extends symmetrically over the passivation layer about the die pad window.

8. The process for fabricating a solder bump according to claim 1, wherein the post is formed by plating copper, and further wherein the cap is formed by plating nickel-tin over the copper.