Variable width low profile gate array input/output architecture

• US 5,760,428 A
• Filed: 01/25/1996
• Issued: 06/02/1998
• Est. Priority Date: 01/25/1996
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Roddy, Stephen P., Colwell, Michael J.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Hardy, David B.
• Application Number:
  US08/596,894
• Time in Patent Office: 859 Days
• Field of Search: 257/203, 257/204, 257/206, 257/207, 257/208
• US Class Current: 257/206
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 27/11807 CMOS gate arrays
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A gate array masterslice having a minimal input/output slot and variable pad pitch architecture is disclosed. In the masterslice, many identical input/output slots ring the periphery of a semiconductor substrate and contain only the special devices necessary for input/output circuits. Each of the input/output slots include (i) a first region containing a plurality of tuning transistors of different sizes, (ii) a second region having one or more PMOS transistors, each of a size greater than any one of the plurality of tuning transistors, (iii) a third region having one or more NMOS transistors, each of a size greater than any one of the plurality of tuning transistors, and (iv) a fourth region containing one or more devices for providing electrostatic discharge protection. One to four PMOS transistors are provided in the second slot region and one to four NMOS transistors are provided in the third slot region. A plurality of bonding pads are provided, at least some of which are electrically connected to at least some of the input/output slots such that the plurality of bonding pads may have a variable bonding pad pitch.

Claims

1. A gate array masterslice formed on a semiconductor substrate, the gate array masterslice comprising:

(a) a plurality of identical input/output slots, each of said input/output slots having;

(i) a first region containing a plurality of tuning transistors of different physical sizes;

(ii) a second region having one or more PMOS transistors, each of a physical size greater than any one of said plurality of tuning transistors;

(iii) a third region having one or more NMOS transistors, each of a physical size greater than any one of said plurality of tuning transistors;

(iv) a fourth region containing one or more devices for providing electrostatic discharge protection; and

(b) a plurality of bonding pads, at least some of which are electrically connected to at least some of said input/output slots, wherein said plurality of bonding pads have a variable bonding pad pitch, and wherein the first region, the second region, the third region and the fourth region are contiguous to one another and the fourth region is closest to a bonding pad of the plurality of bonding pads.

2. The gate array masterslice of claim 1, wherein the variable pad pitch of the plurality of bonding pads varies arbitrarily from pad-to-pad.

3. The gate array masterslice of claim 1, wherein at least some of said bonding pads are electrically connected to input/output circuits that are formed on multiple adjacent input/output slots.

4. The gate array masterslice of claim 1, wherein all of said bonding pads are provided proximate a perimeter of said semiconductor substrate.

5. The gate array masterslice of claim 1, wherein at least some of said bonding pads are provided interior to a perimeter of said semiconductor substrate.

6. The gate array masterslice of claim 1, wherein said plurality of tuning transistors includes at least a first transistor and a second transistor having different gate widths and at least a third transistor and a fourth transistor having different gate lengths.

7. The gate array masterslice of claim 1, further comprising a core region having a plurality of identical base cells, each of which contains multiple transistors of no more than a defined gate length and no more than a defined gate width, wherein each transistor in the first, second, and third regions of said input/output slots has either (i) a gate width that is greater than said defined gate width, (ii) a gate length that is greater than said defined gate length, or (iii) both.

8. The gate array masterslice of claim 1, wherein at least some of said bonding pads are electrically connected to input/output circuits having at least some transistors located in said core region.

9. The gate array masterslice of claim 8, wherein those transistors of the input/output circuits located in the core region are located proximate said plurality of identical input/output slots.

10. The gate array masterslice of claim 1, wherein each of said second and third regions of the plurality of input/output slots contains four or fewer transistors.

11. A gate array masterslice formed on a semiconductor substrate, comprising:

(a) a core region having a plurality of identical base cells, each of which contains multiple transistors;

(b) a plurality of identical input/output slots, each of said input/output slots having;

(i) a first region adjacent said core region and containing a plurality of tuning transistors of different physical sizes;

(ii) a second region adjacent to said first region, and containing at most four PMOS transistors, each of a physical size greater than any one of said plurality of tuning transistors;

(iii) a third region adjacent to said second region, and containing at most four NMOS transistors, each of a physical size greater than any one of said plurality of tuning transistors; and

(iv) a fourth region adjacent to said third region, and containing one or more devices for providing electrostatic discharge protection; and

(c) a plurality of bonding pads, at least some of which are electrically connected to at least some of said input/output slots, wherein the first region, the second region, the third region and the fourth region are contiguous with one another.

12. The gate array masterslice of claim 11, wherein at least some of said bonding pads are electrically connected to input/output circuits that are formed on multiple adjacent input/output slots.

13. The gate array masterslice of claim 11, wherein all of said bonding pads are provided proximate a perimeter of the semiconductor substrate.

14. The gate array masterslice of claim 11, wherein said bonding pads are arranged in multiple rows in a staggered formation.

15. The gate array masterslice of claim 11, wherein at least some of said bonding pads are provided interior to a perimeter of said semiconductor substrate.

16. The gate array masterslice of claim 11, wherein said plurality of tuning transistors includes at least a first transistor and a second transistor having different gate widths and at least a third transistor and fourth transistor having different gate lengths.

17. The gate array masterslice of claim 11, wherein the transistors of each base cell have of no more than a defined gate length and no more than a defined gate width, wherein each transistor in the first, second, and third regions of said input/output slots has either (i) a gate width that is greater than said defined gate width, (ii) a gate length that is greater than said defined gate length, or (iii) both.

18. The gate array masterslice of claim 11, wherein at least some of said bonding pads are electrically connected to input/output circuits having at least some transistors located in said core region.

19. The gate array masterslice of claim 18, wherein those transistors of the input/output circuits located in the core region are located proximate said plurality of identical input/output slots.

20. The gate array masterslice of claim 11 wherein the plurality of bonding pads have a variable bonding pad pitch.

21. A gate array masterslice formed on a semiconductor substrate, comprising:

(a) a core region having a plurality of identical base cells, each of which contains multiple transistors of no more than a defined gate length and no more than a defined gate width;

(b) a plurality of identical input/output slots, each of said input/output slots having;

(i) a first region adjacent to said core region, and containing a plurality of tuning transistors of different physical sizes;

(ii) a second region adjacent to said first region, and having one or more PMOS transistors, each of a physical size greater than any one of said plurality of tuning transistors;

(iii) a third region adjacent to said second region, and having one or more NMOS transistors, each of a physical size greater than any one of said plurality of tuning transistors; and

(iv) a fourth region adjacent to said third region, and containing one or more devices for providing electrostatic discharge protection; and

(c) a plurality of bonding pads, at least some of which are electrically connected to at least some of said input/output slots, wherein each transistor in the first, second, and third regions of said input/output slots has either (i) a gate width that is greater than said defined gate width, (ii) a gate length that is greater than said defined gate length, or (iii) both, and wherein the first, second, third and fourth regions are contiguous with one another.

22. The gate array masterslice of claim 21, wherein at least some of said bonding pads are electrically connected to input/output circuits that are contained in multiple adjacent input/output slots.

23. The gate array masterslice of claim 21, wherein all of said bonding pads are provided proximate the semiconductor substrate periphery.

24. The gate array masterslice of claim 21, wherein at least some of said bonding pads are provided interior to said semiconductor substrate.

25. The gate array masterslice of claim 21, wherein said plurality of tuning transistors includes some transistors which vary in gate width and other transistors which vary in gate length.

26. The gate array masterslice of claim 21, wherein at least some of said bonding pads are electrically connected to input/output circuits having at least some transistors located in said core region.

27. The gate array masterslice of claim 26, wherein those transistors of the input/output circuits located in the core region are located proximate said plurality of identical input/output slots.

28. The gate array masterslice of claim 21, wherein each of said second and third regions of the plurality of input/output slots contains four or fewer transistors.

29. A method of fabricating a gate array masterslice formed on a semiconductor substrate, the method comprising the steps of:

(a) forming a plurality of identical input/output slots on said semiconductor substrate, each of said input/output slots made by;

(i) forming a first region containing a plurality of tuning transistors of different physical sizes;

(ii) forming a second region having one or more PMOS transistors, each of a physical size greater than any one of said plurality of tuning transistors;

(iii) forming a third region having one or more NMOS transistors, each of a physical size greater than any one of said plurality of tuning transistors;

(iv) forming a fourth region containing one or more devices for providing electrostatic discharge protection;

(b) forming a plurality of bonding pads separated from one another by a variable pad pitch, wherein the first, second, third and fourth regions are formed contiguous with one another, and the fourth region is closest to a bonding pad of the plurality of bonding pads.

30. The method of claim 29, wherein the plurality of bonding pads are formed such that the variable pad pitch of the plurality of bonding pads varies arbitrarily from pad-to-pad.

31. The method of claim 29, wherein all of said bonding pads are formed proximate a periphery of said semiconductor substrate.

32. The method of claim 29, wherein said bonding pads are arranged in multiple rows in a staggered formation.

33. The method of claim 29, wherein at least some of said bonding pads are formed interior to a periphery of said semiconductor substrate.

34. The method claim 29, wherein said plurality of tuning transistors are formed such that some transistors vary in gate width and other transistors which vary in gate length.

35. The method of claim 29 further comprising a step of forming electrical connections between at least some of the transistors in the input/output slots to create input/output circuits.

36. The method of claim 34 wherein electrical connections are also formed between at least some transistors in the input/output slots and other transistors in a core region of the gate array masterslice, the core region having a plurality of identical base cells, each of which contains multiple transistors of no more than a defined gate length and no more than a defined gate width.

37. The method of claim 34 wherein each transistor in the first, second, and third regions of said input/output slots is formed with either (i) a gate width that is greater than said defined gate width, (ii) a gate length that is greater than said defined gate length, or (iii) both.

38. The method of making a gate array masterslice of claim 29, wherein each of said second and third regions of the plurality of input/output slots is formed with four or fewer transistors.

39. A gate array masterslice formed on a semiconductor substrate, the gate array masterslice comprising:

(a) a plurality of identical input/output slots, each of said input/output slots having;

(i) a first region containing a plurality of tuning transistors of different physical sizes;

(ii) a second region having one or more PMOS transistors, each of a physical size greater than any one of said plurality of tuning transistors;

(iii) a third region having one or more NMOS transistors, each of a physical size greater than any one of said plurality of tuning transistors, and each of said second and third regions of the plurality of input/output slots contains four or fewer transistors;

(iv) a fourth region containing one or more devices for providing electrostatic discharge protection; and

(b) a plurality of bonding pads, at least some of which are electrically connected to at least some of said input/output slots, wherein said plurality of bonding pads have a variable bonding pad pitch, and wherein the first region, the second region, the third region and the fourth region are contiguous to one another.

40. The gate array masterslice of claim 39, wherein the variable pad pitch of the plurality of bonding pads varies arbitrarily from pad-to-pad.

41. The gate array masterslice of claim 39, wherein at least some of said bonding pads are electrically connected to input/output circuits that are formed on multiple adjacent input/output slots.

42. The gate array masterslice of claim 39, wherein all of said bonding pads are provided proximate a perimeter of said semiconductor substrate.

43. A method of fabricating a gate array masterslice formed on a semiconductor substrate, the method comprising the steps of

(a) forming a plurality of identical input/output slots on said semiconductor substrate, each of said input/output slots made by;

(i) forming a first region containing a plurality of tuning transistors of different physical sizes;

(ii) forming a second region having one or more PMOS transistors, each of a physical size greater than any one of said plurality of tuning transistors;

(iii) forming a third region having one or more NMOS transistors, each of a physical size greater than any one of said plurality of tuning transistors, and each of said second and third regions of the plurality of input/output slots is formed with four or fewer transistors;

(iv) forming a fourth region containing one or more devices for providing electrostatic discharge protection;

(b) forming a plurality of bonding pads separated from one another by a variable pad pitch, wherein the first, second, third and fourth regions are formed contiguous with one another.

44. The method of claim 43, wherein the plurality of bonding pads are formed such that the variable pad pitch of the plurality of bonding pads varies arbitrarily from pad-to-pad.

45. The method of claim 43, wherein all of said bonding pads are formed proximate a periphery of said semiconductor substrate.

46. The method of claim 43, wherein said bonding pads are arranged in multiple rows in a staggered formation.

47. The method of claim 43, wherein at least some of said bonding pads are formed interior to a periphery of said semiconductor substrate.