Use of spacers as floating gates in EEPROM with doubled storage efficiency
First Claim
1. A method of forming side-by-side, double floating gates in an electrically erasable programmable read only memory (EEPROM) with doubled storage efficiency comprising the steps of:
- providing a semiconductor substrate having a layer of silicon oxide;
providing a layer of polycrystalline silicon deposited over said silicon oxide;
patterning said polycrystalline silicon and silicon oxide layers to form a control gate;
doping said control gateion-implanting said substrate using said control gate;
as a mask;
depositing three layers of dielectric over said substrate;
etching said dielectric layers;
growing a tunnel oxide over said dielectric layers;
depositing a second layer of polycrystalline silicon over said substrate;
etching back said polycrystalline silicon layer to form side-by-side double floating gates adjacent to said control gate;
ion-implanting said floating gates; and
ion-implanting said substrate to complete a lightly doped drain (LDD) structure.
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Abstract
A method of forming a high density cell in electrically erasable and programmable read only memory (EEPROM) is disclosed. The doubling efficiency is achieved through providing two floating gates in a single cell, unlike what is found in prior art. While the polysilicon control gate is formed by conventional means, the floating gates are formed through a novel method of forming additional polysilicon spacers which are then coupled with lightly doped drain (LDD) regions to function as floating gates. Furthermore, the cell is turned on and off through the modulation of the LDD resistance and not through charge saturation methods of prior art. Finally, it is shown that through the use of two floating gates, rather than one, two bits of information can be stored in one cell with the concomitant advantage of doubled efficiency.
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Citations
31 Claims
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1. A method of forming side-by-side, double floating gates in an electrically erasable programmable read only memory (EEPROM) with doubled storage efficiency comprising the steps of:
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providing a semiconductor substrate having a layer of silicon oxide; providing a layer of polycrystalline silicon deposited over said silicon oxide; patterning said polycrystalline silicon and silicon oxide layers to form a control gate; doping said control gate ion-implanting said substrate using said control gate;
as a mask;depositing three layers of dielectric over said substrate; etching said dielectric layers; growing a tunnel oxide over said dielectric layers;
depositing a second layer of polycrystalline silicon over said substrate;etching back said polycrystalline silicon layer to form side-by-side double floating gates adjacent to said control gate; ion-implanting said floating gates; and ion-implanting said substrate to complete a lightly doped drain (LDD) structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A side-by-side structure for double floating gates in an EEPROM cell comprising:
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a semiconductor substrate containing lightly doped regions formed by two implants and separated by a channel region; a control gate formed over but insulated from said channel region; two floating gates positioned side-by-side on either side of the control gate; a double bit storage structure for a single memory cell. - View Dependent Claims (28, 29, 30, 31)
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Specification