Use of spacers as floating gates in EEPROM with doubled storage efficiency

• US 5,760,435 A
• Filed: 04/22/1996
• Issued: 06/02/1998
• Est. Priority Date: 04/22/1996
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Pte Ltd (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Pan, Yang
• Primary Examiner(s): Wojciechowicz, Eward
• Application Number:
  US08/635,993
• Time in Patent Office: 771 Days
• Field of Search: 257/316, 257/321, 257/314, 257/315, 257/403, 438/157, 438/176, 438/267, 438/522, 438/694
• US Class Current: 257/314
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation

Abstract

A method of forming a high density cell in electrically erasable and programmable read only memory (EEPROM) is disclosed. The doubling efficiency is achieved through providing two floating gates in a single cell, unlike what is found in prior art. While the polysilicon control gate is formed by conventional means, the floating gates are formed through a novel method of forming additional polysilicon spacers which are then coupled with lightly doped drain (LDD) regions to function as floating gates. Furthermore, the cell is turned on and off through the modulation of the LDD resistance and not through charge saturation methods of prior art. Finally, it is shown that through the use of two floating gates, rather than one, two bits of information can be stored in one cell with the concomitant advantage of doubled efficiency.

Claims

1. A method of forming side-by-side, double floating gates in an electrically erasable programmable read only memory (EEPROM) with doubled storage efficiency comprising the steps of:

providing a semiconductor substrate having a layer of silicon oxide;

providing a layer of polycrystalline silicon deposited over said silicon oxide;

patterning said polycrystalline silicon and silicon oxide layers to form a control gate;

doping said control gate

ion-implanting said substrate using said control gate;

as a mask;

depositing three layers of dielectric over said substrate;

etching said dielectric layers;

growing a tunnel oxide over said dielectric layers;

depositing a second layer of polycrystalline silicon over said substrate;

etching back said polycrystalline silicon layer to form side-by-side double floating gates adjacent to said control gate;

ion-implanting said floating gates; and

ion-implanting said substrate to complete a lightly doped drain (LDD) structure.

2. The method of claim 1, wherein the thickness of the silicon oxide layer is in between about 100 to 400 Angstroms (Å

).

3. The method of claim 1, wherein the thickness of the polycrystalline silicon layer is in between about 2,000 to 4,000 Å

.

4. The method of claim 1, wherein said control gate is doped with phosphorous.

5. The method of claim 4, wherein said doping dosage is in between about 1×

10¹⁵ to 1×

10¹⁶ atoms/cm².

6. The method of claim 4, wherein the energy level of said doping is in between about 60 to 70 KEV.

7. The method of claim 1, wherein said ion-implant of the substrate is phosphorus.

8. The method of claim 7, wherein the concentration of said ion-implant is in between about 1×

10¹³ to 1×

10¹³ atoms/cm².

9. The method of claim 7, wherein the energy of said ion-implant is in between about 20 to 100 KEV.

10. The method of claim 1, wherein the first layer of said dielectrics is silicon oxide.

11. The method of claim 10, wherein the thickness of said first layer of silicon oxide is between about 100 to 150 Å

.

12. The method of claim 1, wherein the second layer of said dielectrics is silicon nitride (SiN).

13. The method of claim 12, wherein the thickness of said second layer of SiN is between about 100 to 150 Å

.

14. The method of claim 1, wherein the third layer of said dielectrics is silicon oxide.

15. The method of claim 14, wherein the thickness of said third layer of dielectric is between about 100 to 150 Å

.

16. The method of claim 1, wherein the said dielectric layers are anisotropically etched to form ONO spacers.

17. The method of claim 1, wherein the thickness of said tunnel oxide is between about 80 to 120 Å

.

18. The method of claim 1, wherein the thickness of said second layer of polycrystalline silicon is between about 2,000 to 4,000 Å

.

19. The method of claim 18, wherein said second polycrystalline silicon is etched back to form floating gate spacers.

20. The method of claim 1, wherein said floating gates are ion-implanted with phosphorus.

21. The method of claim 20, wherein the concentration of said ion-implant is between about 1×

10¹⁵ to 1×

10¹⁶ atoms/cm².

22. The method of claim 20, wherein the energy of said ion-implant is between about 20 to 50 KEV.

23. The method of claim 1, wherein said ion-implant of the substrate is accomplished by using the side-by-side gates as the mask.

24. The method of claim 23, wherein said ion-implant is arsenic.

25. The method of claim 23, wherein the concentration of said arsenic ion-implant is in between about 1×

10¹⁵ to 1×

10¹⁶ atoms/cm².

26. The method of claim 23, wherein the energy of said arsenic ion-implant is between about 20 to 80 KEV.

27. A side-by-side structure for double floating gates in an EEPROM cell comprising:

a semiconductor substrate containing lightly doped regions formed by two implants and separated by a channel region;

a control gate formed over but insulated from said channel region;

two floating gates positioned side-by-side on either side of the control gate;

a double bit storage structure for a single memory cell.

28. The structure of claim 27, wherein said substrate is ion-implanted with arsenic.

29. The structure of claim 28, wherein said floating gates are ion-implanted with phosphorus.

30. The structure of claim 28, wherein said control gate is ion-implanted with phosphorous.

31. The structure of claim 27, wherein said floating gates are insulated from said control gate by an insulating layer of thickness in between about 100 to 400 Angstroms.