EEPROM cell and process for formation thereof

• US 5,760,436 A
• Filed: 10/10/1996
• Issued: 06/02/1998
• Est. Priority Date: 12/07/1994
• Status: Expired due to Term

• Current Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Original Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Inventors: Chung, Seong-Woo
• Primary Examiner(s): Levy, Stuart S.
• Assistant Examiner(s): Giordana, Adriana
• Application Number:
  US08/729,292
• Time in Patent Office: 600 Days
• Field of Search: 257/314-322, 365/185
• US Class Current: 257/314
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A flash EEPROM cell structure and a method for forming it. The method of forming the EEPROM cell includes the steps of: forming a plurality of trenches on a substrate, the trenches being filled with an insulating layer; forming bit lines between the trenches and on the substrate; forming an insulating layer on the bit lines; forming a floating gate, with at least one side of it contacting with the bit lines; and simultaneously forming a control gate and an erasing gate. The control gate and the erasing gate cross the bit lines and the floating gate. The erasing gate also extends over the trenches. The floating gate and the erasing gate extend down into the trenches.

Claims

1. An electrically erasable programmable read only memory (EEPROM) having a plurality of cells, the EEPROM comprising:

a substrate having trenches therein;

a first insulating layer in the trenches;

impurity regions on the substrate located between the trenches;

second insulating layers on the impurity regions, respectively;

a gate insulating layer adjacent to the impurity regions and formed on the substrate extending partially into the trenches over the first insulating layer;

first gates on the gate insulating layer, the first gates;

being positioned between the trenches; and

having a portion of a side contiguous with the second insulating layers so as to partially overlap said impurity regions, respectively;

non-overlapping second gates and third gates, there being a second gate and at least one third gate for each given first gate, said second gates not overlapping said third gates;

the second gates being located over the substrate and being located so as to cross over the first gates, respectively; and

the third gates being located over the substrate, over the trenches, between the second gates, and being located so as to cross over the first gates.

2. An EEPROM as in claim 1, wherein the thickness of the first insulating layer is less than or equal to the depth of the trenches.

3. An EEPROM as in claim 1, wherein said first gates and said gate insulating layer extend down into said trenches, respectively.

4. An EEPROM as in claim 1, wherein the thickness of the first insulating layer is less than the depth of the trenches.

5. An EEPROM as in claim 1, wherein the third gates are partially located in said trenches.

6. An EEPROM as in claim 1, wherein said impurity regions are bit lines, said first gates are floating gates, said second gates are control gates and said third gates are erasing gates.

7. An EEPROM as in claim 6, wherein the floating gates, the control gates, and the erasing gates are polysilicon.

8. An EEPROM as in claim 6, wherein the control gates are parallel to the erasing gates.

9. An EEPROM as in claim 6, wherein the bit lines are parallel to the floating gates and are perpendicular to the control gates and the erasing gates.