Electronic package with strain relief means

• US 5,760,465 A
• Filed: 02/01/1996
• Issued: 06/02/1998
• Est. Priority Date: 02/01/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Guo, Yifan, Johnson, Eric Arthur, Alcoe, David James, Anderson, Steven Wayne
• Primary Examiner(s): OSTROWSKI, DAVID M
• Application Number:
  US08/595,108
• Time in Patent Office: 852 Days
• Field of Search: 257/669, 257/701, 257/674, 257/672, 257/676, 257/735, 257/738, 361/749, 361/776, 439/67
• US Class Current: 257/669
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/83851 being an anisotropic conductive adhesive
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/49572 consisting of thin flexible metallic tape with or without a film carrier H01L23/49503 - H01L23/49568 and H01L23/49575 - H01L23/49579 take precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/86 using tape automated bonding [TAB]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An electronic package which includes a flexible substrate, stiffener and chip. The chip is bonded to the substrate, which was secured to the stiffener. Strain relief means are utilized at various locations in the package to prevent problems (e.g., tape "wrinkling") associated with relatively large differences in coefficients of thermal expansion between the package'"'"'s various elements.

Claims

1. In an electronic package including a stiffener member, a flexible circuitized substrate secured to said stiffener member and including at least a first dielectric layer, at least one conductive layer located on said first dielectric layer and further including a plurality of signal lines occupying a first plane and each having a projecting lead portion as part thereof which projects a predetermined distance from said first dielectric layer, selected ones of said signal lines adapted for being electrically connected to respective ones of external conductive elements when said elements are positioned on said flexible circuitized substrate, and a semiconductor device including a plurality of contact sites thereon, selected ones of said contact sites electrically coupled to respective ones of said projecting lead portions of said signal lines and spacedly positioned from said stiffener, the improvement wherein said projecting lead portions of said selected ones of said signal lines of said flexible circuitized substrate are bent in a direction substantially toward said semiconductor device and occupy a different plane than said first plane of said signal lines to thereby include strain relief means therein at a location adjacent but not at the point of said electrical coupling between said projecting lead portions and said contact sites of said semiconductor device.

2. The package of claim 1 further including a heat sinking member, said stiffener member being secured to said heat sinking member.

3. The package of claim 2 wherein said stiffener member includes at least one tab portion for being secured about at least part of said heat sinking member to provide the securement of said stiffener to said heat sinking member.

4. The package of claim 3 wherein the material for said stiffener member and said heat sinking member is selected from the group consisting essentially of copper, aluminum, and alloys thereof.

5. The package of claim 2 wherein said semiconductor device is thermally bonded to said heat sinking member.

6. The package of claim 5 wherein said heat sinking member includes strain relief means therein substantially at the location where said semiconductor device is bonded to said heat sinking member.

7. The package of claim 6 wherein said strain relief means within said heat sinking member comprises a portion of reduced thickness within said heat sinking member.

8. The package of claim 5 wherein said heat sinking member includes a plurality of channels therein.

9. The package of claim 8 wherein said semiconductor device is bonded to said heat sinking member using a thermal adhesive, at least some of said thermal adhesive being located within said channels.

10. The package of claim 1 wherein said flexible circuitized substrate also includes an indentation therein as part of said strain relief means.

11. The package of claim 1 wherein said flexible circuitized substrate includes a second layer of dielectric material positioned on said conductive layer and substantially covering said conductive layer except for said projecting lead portions of said signal lines.

12. The package of claim 11 wherein said second layer of dielectric material includes a feathered edge portion.

13. The package of claim 12 wherein said first and second layers of dielectric material are comprised of polyimide.

14. The package of claim 11 further including a quantity of encapsulant material substantially covering said second layer of dielectric material at the location of said flexible circuitized substrate between said semiconductor device and said stiffener member.

15. The package of claim 14 wherein said encapsulant material is of a substantially tapered configuration, having a greater thickness in the location of said flexible circuitized substrate immediately adjacent said semiconductor device.

16. The package of claim 1 further including a quantity of encapsulant material substantially covering said conductive layer at the location of said flexible circuitized substrate between said semiconductor device and said stiffener member.

17. The package of claim 16 wherein said encapsulant material is of a substantially tapered configuration, having a greater thickness in the location of said flexible circuitized substrate immediately adjacent said semiconductor device.

18. The package of claim 1 wherein said strain relief means comprises a moderated thermal expansivity region on said flexible circuitized substrate relative to said chip.

19. The package of claim 1 further including a plurality of said electrical conductive elements spacedly positioned on said flexible circuitized substrate.

20. The package of claim 19 wherein said conductive elements are comprised of solder.

21. An information handling system comprising an electronic package including a stiffener member, a flexible circuitized substrate secured to said stiffener member and including at least a first dielectric layer, at least one conductive layer located on said first dielectric layer and including a plurality of signal lines occupying a first plane and each having a projecting lead portion as part thereof which projects a predetermined distance from said first dielectric layer, selected ones of said signal lines adapted for being electrically connected to respective ones of external conductive elements when said external conductive elements are positioned on said flexible circuitized substrate, and a semiconductor device including a plurality of contact sites thereon, selected ones of said contact sites electrically coupled to respective ones of said projecting lead portions of said signal lines and spacedly positioned from said stiffener, said projecting lead portions of said signal lines of said flexible circuitized substrate being bent in a direction substantially toward said semiconductor device to occupy a different plane than said first plane of said signal lines to thereby include strain relief means therein at a location adjacent but not at the point of said electrical coupling between said projecting lead portions and said contact sites of said semiconductor device.