Multi-layer electrical interconnection structures

• US 5,760,470 A
• Filed: 05/23/1995
• Issued: 06/02/1998
• Est. Priority Date: 02/10/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Display Technology, Inc. (PixTech, Inc.)
• Inventors: Stansbury, Darryl M.
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US08/447,747
• Time in Patent Office: 1,106 Days
• Field of Search: 257/700, 257/690, 257/778, 257/784, 257/782, 257/780
• US Class Current: 257/690
• CPC Class Codes: H01J 2329/00 Electron emission display panels, e.g. field emission display panels
• CPC Class Codes: H01J 2329/8625 Spacing members
• CPC Class Codes: H01J 2329/92 Means forming part of the display panel for the purpose of providing electrical connection to it
• CPC Class Codes: H01J 29/028 Mounting or supporting arrangements for flat panel cathode ray tubes, e.g. spacers particularly relating to electrodes
• CPC Class Codes: H01J 29/92 Means forming part of the tube for the purpose of providing electrical connection to it
• CPC Class Codes: H01J 9/185 of flat panel display devices, e.g. by using spacers
• CPC Class Codes: H01J 9/241 the vessel being for a flat panel display H01J9/261 takes precedence; flat discharge lamps H01J9/248
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/78 Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/85 using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: Y10T 29/49144 : by metal fusion
• CPC Class Codes: Y10T 29/49162 : by using wire as conductive path

Abstract

A flat-panel field emission display comprises a luminescent faceplate, a rigid backplate, and an interposed or sandwiched emitter or cathode plate. A dielectric connector ridge is screen-printed over the faceplate'"'"'s rear surface. Upper and lower level conductors are then screen printed over the faceplate. The lower-level conductors are applied directly on the faceplate rear surface. The upper-level conductors are applied atop the connector ridge. A plurality of bond wire interconnections extend between individual screen-printed conductors of the upper and lower levels. The bond wire interconnections create inter-level electrical interconnections between said individual screen-printed conductors. The cathode plate is positioned over the connector ridge. The cathode plate has a plurality of die bond pads facing the faceplate rear surface and aligned with the upper-level conductors. A plurality of conductive bonds such as flip-chip connections are positioned between the die bond pads and the facing upper-level conductors.

Claims

1. A multi-layer electrical interconnection structure comprising:

a substrate;

a plurality of conductors which are screen printed over the substrate, the screen-printed conductors having upper-level portions and lower-level portions;

a plurality of bond wire interconnections extending between the upper-level portions and the lower-level portions of individual screen-printed conductors, the bond wire interconnections creating inter-level electrical connections between the upper-level and lower-level portions of said individual screen-printed conductors; and

further comprising;

a semiconductor die positioned over the substrate, the semiconductor die having die bond pads which face the substrate, the die bond pads being aligned with the upper-level portions of said individual screen-printed conductors; and

conductive bonds between the aligned die bond pads and the upper-level portions of said individual screen-printed conductors.

2. A multi-layer electrical interconnection structure comprising:

a substrate;

a plurality of conductors which are screen printed over the substrate, the screen-printed conductors having upper-level portions and lower-level portions;

a plurality of bond wire interconnections extending between the upper-level portions and the lower-level portions of individual screen-printed conductors, the bond wire interconnections creating inter-level electrical connections between the upper-level and lower-level portions of said individual screen-printed conductors; and

further comprising;

a semiconductor die positioned over the substrate, the semiconductor die having die bond pads which face the substrate, the die bond pads being aligned with the upper-level portions of said individual screen-printed conductors; and

conductive metal bumps between the aligned die bond pads and the upper-level portions of said individual screen-printed conductors, the conductive metal bumps forming conductive bonds between the aligned die bond pads and the upper-level portions of said individual screen-printed conductors.

3. A multi-layer electrical interconnection structure comprising:

a substrate;

a screen-printed dielectric layer over the substrate;

a lower level of screen-printed conductors over the substrate at a first elevation;

an upper level of screen-printed conductors overlying the screen-printed dielectric layer at a second elevation which is greater than the first elevation;

a plurality of bond wire interconnections extending between individual screen-printed conductors of the upper and lower levels, the bond wire interconnections creating inter-level electrical connections between said individual screen-printed conductors of the upper and lower levels; and

further comprising a semiconductor die having a plurality of die bond pads facing the substrate and aligned with individual upper-level screen-printed conductors, the die bond pads being conductively bonded to said individual upper-level screen-printed conductors.

4. A multi-layer electrical interconnection structure comprising:

a substrate;

a screen-printed dielectric layer over the substrate;

a lower level of screen-printed conductors over the substrate at a first elevation;

an upper level of screen-printed conductors overlying the screen-printed dielectric layer at a second elevation which is greater than the first elevation;

a plurality of bond wire interconnections extending between individual screen-printed conductors of the upper and lower levels, the bond wire interconnections creating inter-level electrical connections between said individual screen-printed conductors of the upper and lower levels; and

further comprising;

a semiconductor die having a plurality of die bond pads facing the substrate and aligned with individual upper-level screen-printed conductors; and

a plurality of conductive metal bumps between the aligned die bond pads and individual upper-level screen-printed conductors, the conductive metal bumps forming conductive bonds between the die bond pads and said individual upper-level screen-printed conductors.

5. A multi-layer electrical interconnection structure comprising:

a substrate;

a screen-printed dielectric layer over the substrate;

a lower level of screen-printed conductors over the substrate at a first elevation;

an upper level of screen-printed conductors overlying the screen-printed dielectric layer at a second elevation which is greater than the first elevation;

a plurality of bond wire interconnections extending between individual screen-printed conductors of the upper and lower levels, the bond wire interconnections creating inter-level electrical connections between said individual screen-printed conductors of the upper and lower levels; and

further comprising;

a semiconductor die having a plurality of die bond pads facing the substrate and aligned with the individual upper-level screen-printed conductors; and

a plurality of flip-chip connections between the die bond pads and said individual upper-level screen-printed conductors.

6. A multi-layer electrical interconnection structure comprising:

a substrate;

a screen-printed dielectric layer over the substrate;

a lower level of screen-printed conductors over the substrate at a first elevation;

an upper level of screen-printed conductors overlying the screen-printed dielectric layer at a second elevation which is greater than the first elevation;

a plurality of bond wire interconnections extending between individual screen-printed conductors of the upper and lower levels, the bond wire interconnections creating inter-level electrical connections between said individual screen-printed conductors of the upper and lower levels; and

further comprising;

a semiconductor die having a plurality of die bond pads facing the substrate; and

a plurality of bond wire stubs bonded either to said individual upper-level screen-printed conductors or to the die bond pads, the bond wire stubs having projecting tails of bond wire which are interposed between said individual upper-level screen-printed conductors and the die bond pads to form conductive bonds therebetween.

7. A multi-layer electrical interconnection structure comprising:

a substrate;

a screen-printed dielectric layer over the substrate;

a lower level of screen-printed conductors over the substrate at a first elevation;

an upper level of screen-printed conductors overlying the screen-printed dielectric layer at a second elevation which is greater than the first elevation;

a plurality of bond wire interconnections extending between individual screen-printed conductors of the upper and lower levels, the bond wire interconnections creating inter-level electrical connections between said individual screen-printed conductors of the upper and lower levels; and

further comprising;

a semiconductor die having a plurality of die bond pads facing the substrate;

a plurality of bond wire wedge bonds formed either on said individual upper-level screen-printed conductors or on the die bond pads; and

tails of bond wire which project from the wedge bonds, the bond wire tails being interposed between said individual upper-level screen-printed conductors and the die bond pads to form conductive bonds therebetween.

8. A multi-layer interconnection structure comprising:

a substrate having a planar surface;

a connector ridge formed over the substrate;

a lower level of conductors applied over the substrate;

an upper level of conductors applied atop the connector ridge;

a plurality of bond wire interconnections between individual conductors of the upper and lower levels, the bond wire interconnections creating inter-level electrical interconnections between said individual conductors of the upper and lower levels;

a semiconductor die positioned over the connector ridge, the semiconductor die having a plurality of die bond pads facing the substrate and aligned with the upper-level conductors; and

a plurality of conductive bonds between individual die bond pads and the facing upper-level conductors.

9. A multi-layer interconnection structure as recited in claim 8, the interconnection structure further comprising conductive metal bumps between said die bond pads and the facing upper-level conductors, the conductive metal bumps forming the conductive bonds.

10. A multi-layer interconnection structure as recited in claim 8, the interconnection structure further comprising a plurality of flip-chip connections forming the conductive bonds.

11. A multi-layer interconnection structure as recited in claim 8, and further comprising bond wire stubs bonded either to individual upper-level conductors or to said individual die bond pads, the bond wire stubs having projecting tails of bond wire which are interposed between said individual upper-level conductors and said individual die bond pads to form the conductive bonds.

12. A multi-layer interconnection structure as recited in claim 8 and further comprising:

a plurality of bond wire wedge bonds formed either on individual upper-level conductors or on said individual die bond pads; and

tails of bond wire which project from the wedge bonds, the bond wire tails being interposed between said individual upper-level conductors and said individual die bond pads to form the conductive bonds.