Interconnect run between a first point and a second point in a semiconductor device for reducing electromigration failure

• US 5,760,476 A
• Filed: 10/15/1996
• Issued: 06/02/1998
• Est. Priority Date: 08/01/1994
• Status: Expired due to Fees

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Varker, Charles J., Dreyer, Michael L., Zirkle, Thomas E.
• Primary Examiner(s): Thomas, T.
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/729,200
• Time in Patent Office: 595 Days
• Field of Search: 257/773, 257/775, 257/765-767, 257/920, 257/923, 257/758, 257/740, 257/786
• US Class Current: 257/767
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/92 Conductor layers on different levels connected in parallel, e.g. to reduce resistance

Abstract

In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36, 38) is disposed between two of the fingers (16,18,20) for dividing current flow. In a second approach, an interconnect level (50) is formed of a polycrystalline material and connects two points in the semiconductor device using essentially only a plurality of branches (52) each having a linewidth (W) less than the median grain size of the polycrystalline material. In a third approach, an interconnect run (60) consists essentially of a plurality of upper and lower straps (62, 64) connected by a plurality of interlevel connectors (66) so that a chain is provided which connects substantially the full length between two points in the semiconductor device.

Claims

1. An interconnect run between and electrically coupling a first point and a second point in a semiconductor device that reduces electromigration failure, consisting essentially of a plurality of upper straps connected to a plurality of lower straps by a plurality of interlevel connectors substantially resistant to electromigration, said plurality of lower straps comprising at least a first lower strap, a second lower strap and a third lower strap, and said plurality of interlevel connectors comprising at least a first interlevel connector and a second interlevel connector, wherein the first lower strap is connected to said first point and to the first interlevel connector and the second lower strap is connected to said second point and to the second interlevel connector and the second lower strap is not connected to the first lower strap, and wherein each of said plurality of upper straps is connected to only two of said plurality of lower straps and each of said plurality of lower straps other than the first lower strap and the second lower strap is connected to only two of said plurality of upper straps, and wherein none of said plurality of upper straps or said plurality of lower straps has a length greater than about 12 microns.

2. The interconnect run of claim 1 wherein a distance from one of said interlevel connectors to a next closest one of said interlevel connectors is less than about 6 microns.

3. The interconnect run of claim 1 wherein:

each of said interlevel connectors is a via comprising tungsten; and

said upper straps and said lower straps comprise aluminum.

4. The interconnect run of claim 1 wherein said full length of said interconnect run is more than about 80 microns.

6. The interconnect run of claim 1 wherein a distance from one of said interlevel connectors to a next closest one of said interlevel connectors is less than about 6 microns.

7. The interconnect run of claim 1 wherein:

each of said interlevel connectors is a via comprising tungsten; and

said upper straps and said lower straps comprise aluminum.

8. The interconnect run of claim 1 wherein said full length of said interconnect run is more than about 80 microns.

5. An interconnect run between and electrically coupling a first point and a second point in a semiconductor device that reduces electromigration failure, consisting essentially of a plurality of upper straps connected to a plurality of lower straps by a plurality of interlevel connectors substantially resistant to electromigration, said plurality of upper straps comprising at least a first upper strap, a second upper strap and a third upper strap, and said plurality of interlevel connectors comprising at least a first interlevel connector and a second interlevel connector, wherein the first upper strap is connected to said first point and to the first interlevel connector and the second upper strap is connected to said second point and to the second interlevel connector and the second upper strap is not connected to the first upper strap, and wherein each of said plurality of upper straps other than the first upper strap and the second upper strap is connected to only two of said plurality of lower straps and each of said plurality of lower straps is connected to only two of said plurality of upper straps, and wherein none of said plurality of upper straps or said plurality of lower straps has a length greater than about 12 microns.