DC offset compensation device

• US 5,760,629 A
• Filed: 07/18/1996
• Issued: 06/02/1998
• Est. Priority Date: 08/08/1995
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Takai, Hitoshi, Urabe, Yoshio, Tatsuta, Akihiro, Yamasaki, Hidetoshi
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US08/683,309
• Time in Patent Office: 684 Days
• Field of Search: 327/306, 327/307, 327/362, 327/551
• US Class Current: 327/307
• CPC Class Codes: H03F 1/30 Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in differential amplifiers H03F3/45479

Abstract

A level detector 2 detects variation of the amplitude of an input signal a to output a level signal b representing HIGH or LOW in order to define the head portion of the input circuit a. A time constant control signal 3 generates a time constant control signal c based on the level signal b to control a time constant of an estimator 4 so as to make the time constant small for a prescribed period from a time when the level signal b varies from HIGH to LOW. The estimator 4 estimates DC offset included in the input signal a with the a time constant variation according to the time constant control signal c to output an estimate d. A compensator 1 subtracts the estimate d from the input signal a to obtain a compensation output. Therefore, in the estimator 4, the speed of estimating the DC offset is different between a period corresponding to the head portion of the input signal a and other periods. Thus, a DC offset compensation device can be configured to be capable of fast DC offset compensation at the head portion of the input signal a and stable DC offset compensation at the other portions.

Claims

1. A DC offset compensation device for compensating DC offset included in an input signal, said device comprising:

level detecting means for detecting variation in amplitude of the input signal to generate and output a level signal which defines a head portion of the input signal;

time constant controlling means for generating and for outputting a time constant control signal based on the level signal;

compensating means for subtracting an estimate of the DC offset from a value of the input signal to output a compensation output; and

estimating means for receiving the compensation output, for estimating the DC offset of the input signal based on the compensation output with a time constant which varies according to the time constant control signal, and for outputting the estimate to feedback to said compensating means.

2. The DC offset compensation device according to claim 1, wherein

the level signal is a binary signal having a first value or a second value;

a first time is a time when the level signal varies from the first value to the second value, and

a second time is a time lapsed for a prescribed time from the first time in a state that the level signal has the second value, and

said time constant controlling means is for outputting the time constant control signal for maximizing the time constant during a period when the level signal maintains the second value after the second time.

3. The DC offset compensation device according to claim 2, wherein

said time constant controlling means is for generating and outputting the time constant control signal for minimizing the time constant during a period between the first time and the second time.

4. The DC offset compensation device according to claim 2, wherein

said time constant controlling means is for generating and outputting the time constant control signal for monotonically increasing the time constant from a minimum to a maximum, continuously or stepwise.

5. The DC offset compensation device according to claim 1, wherein

said estimating means comprises:

a first integrator for integrating the compensation output to output a first integration value;

a comparator for deciding an upper limit reference value and a lower limit reference value based on the time constant control signal and comparing the first integration value with the decided upper limit reference value and lower limit reference value to output a comparison output; and

a second integrator for integrating the comparison output to output the estimate;

wherein

said comparator outputs the comparison output

as 0 when the first integration value is more than the lower limit reference value and less than the upper limit reference value,

as +1 when the first integration value is not less than the upper limit reference value, and

as -1 when the first integration value is not more than the lower limit reference value; and

said first integrator resets the first integration value when the comparison output is +1 or -1.

6. The DC offset compensation device according to claim 5, wherein

said first integrator comprises:

a quantizer for quantizing the compensation output according to the compensation output'"'"'s amplitude and for generating and outputting a quantization signal;

a register for holding the first integration value; and

an adder for adding the quantization signal to the first integration value held by said register and taking an addition result as the first integration value.

7. The DC offset compensation device according to claim 5, wherein

said first integrator comprises:

a quantizer for quantizing the compensation output according to the compensation output'"'"'s amplitude and for generating and outputting a quantization signal; and

an up/down counter generating and outputting the first integration value based on the quantization signal;

wherein

said up/down counter changes a counting direction based on the quantization signal.

8. The DC offset compensation device according to claim 6, wherein

said quantizer is for quantizing to two values of {+1, -1} or three values {+1, 0, -1} according to the amplitude of the compensation output to output the quantization signal.

9. The DC offset compensation device according to claim 5, wherein

said second integrator comprises:

a register for holding the estimate; and

an adder for adding the comparison output to the estimation held by said register and for taking an addition result as the estimate.

10. The DC offset compensation device according to claim 5, wherein

said second integrator comprises an up/down counter for generating and outputting the estimate based on the comparison output, and

said up/down counter changes a counting direction based on the inputted comparison output.

11. The DC offset compensation device according to claim 1, wherein

said estimating means comprises:

a correction constant generator for generating a correction constant according to the time constant control signal,

an adder/subtractor for selecting addition or subtraction according to the compensation output, and

a register for holding the estimate;

wherein

said adder/subtractor

adds the estimate held by said register to the correction constant to output an addition result as an estimate when the compensation output is positive, and

subtracts the correction constant from the estimate held by said register to output a subtraction result as an estimate when the compensation output is negative.

12. The DC offset compensation device according to claim 1, wherein

said estimating means comprises:

a correction constant generator for generating a positive correction constant and a negative correction constant according to the time constant control signal to output either one of the correction constants according to the compensation output,

a register for holding the estimate, and

an adder for adding the correction constant outputted from said correction constant generator to the estimate held by said register to output an addition result as the estimate;

wherein

said correction constant generator outputs

the positive correction constant when the compensation output is positive, and

the negative correction constant when the compensation output is negative.

15. The DC offset compensation device according to claim 1, wherein

said level detecting means comprises:

a high pass filter generating and outputting a high pass signal from which a low frequency component of the input signal is eliminated,

a rectifier for generating and outputting a rectification signal obtained by rectifying the high pass signal, and

a smoothing unit for generating and outputting a smooth output with a time variation of the rectification signal reduced; and

said level detecting means is for outputting the level signal based on the smooth output.

16. The DC offset compensation device according to claim 15, wherein

the level signal is a binary signal having a first value or a second value;

and

said level detecting means is for comparing the smooth output and a prescribed reference value and outputs the level signal as the second value when the smooth output is continuously greater than the prescribed reference value for a prescribed judging time and outputs the level signal as the first value otherwise.

20. The DC offset compensation device according to claim 1, wherein

said level detecting means comprises:

a high pass filter for generating and outputting a high pass signal from which a low frequency component of the input signal is eliminated,

a rectifier for generating and outputting a rectification output obtained by rectifying the high pass signal,

a smoothing unit for generating and outputting a smooth output with a time variation of the rectification output reduced,

a threshold generating means for time-average the smooth output and for generating and outputting a threshold formed by multiplying the time-averaged smooth output by a prescribed coefficient not less than 1, and

a judging means for comparing the smooth output inputted by said smoothing unit with the threshold and generating and outputting a judgment output representing whether the smooth output is greater or less than the threshold; and

said level detecting means is for outputting the level signal based on the judgment output.

21. The DC offset compensation device according to claim 20, wherein

the level signal is a binary signal having a first value or a second value;

and

said level detecting means is for outputting the level signal as the second value when the judgment output continuously becomes a large value for a prescribed judging time and is for outputting the level signal as the first value otherwise.

22. The DC offset compensation device according to claim 1, wherein

the level signal is a binary signal having a first value or a second value;

said level detecting means comprises;

a high pass filter for generating and outputting a high pass signal from which a low frequency component of the input signal is eliminated,

a rectifier for generating and outputting a rectification output obtained by rectifying the high pass signal,

a smoothing unit for generating and outputting a smooth output with a time variation of the rectification output reduced,

a threshold generating means for time-average the smooth output and for generating and outputting a threshold formed by multiplying the time-averaged smooth output by a prescribed coefficient not less than 1,

a delay means for generating and outputting a delayed threshold obtained by delaying the threshold for not less than a prescribed judging time, and

a judging means for comparing the smooth output with the delayed threshold and generating and outputting a judgment output representing whether the smooth output is greater or less than the threshold; and

said level detecting means is for outputting the level signal as the second value when the judgment output continuously becomes a large value for the prescribed judging time and is for outputting the level signal as the first value otherwise.

13. A DC offset compensation device for compensating DC offset included in an input signal, said device comprising:

level detecting means for detecting variation in amplitude of the input signal to generate and output a level signal which defines a head portion of the input signal;

time constant controlling means for generating and for outputting a time constant control signal based on the level signal;

compensating means for subtracting an estimate of the DC offset from a value of the input signal to output a compensation output; and

estimating means for receiving the input signal, for estimating the DC offset of the input signal with a time constant which varies according to the time constant control signal, and for outputting the estimate to feed forward to said compensating means.

14. The DC offset compensation device according to claim 13, wherein

said estimating means is a low-pass filter for changing a tap coefficient according to the time constant control signal.

17. A DC offset compensation device for compensating DC offset included in an input signal, said device comprising:

compensating means for subtracting an estimate of the DC offset from a value of the input signal to output a compensation output;

level detecting means for detecting variation in amplitude of the compensation output to generate and output a level signal which defines a head portion of the input signal;

time constant controlling means for generating and outputting a time constant control signal based on the level signal; and

estimating means for receiving the compensation output, for estimating the DC offset of the input signal based on the compensation output with a time constant which varies according to the time constant control signal, and for outputting the estimate to feedback to said compensating means.

18. The DC offset compensation device according to claim 17, wherein

said level detecting means comprises:

a rectifier for generating and outputting a rectification output obtained by rectifying said compensation output, and

a smoothing unit for generating and outputting a smooth output with a time variation of the rectification output reduced; and

said level detecting means is for outputting the level signal based on the smooth output.

19. The DC offset compensation device according to claim 18, wherein

the level signal is a binary signal having a first value or a second value;

and

said level detecting means is for comparing the smooth output and a prescribed reference value and outputs the level signal as the second value when the smooth output is continuously greater than the prescribed reference value for a prescribed judging time and outputs the level signal as the first value otherwise.