Phase-locked loop for clock recovery
First Claim
1. A circuit comprising:
- a pulse generator generating a pulse signal of a predetermined pulse width at each level transition of an input signal having an NRZ (non return to zero) signaling method;
a detector detecting a voltage signal corresponding to a voltage of a periodic signal at a time corresponding to each pulse of the pulse signal;
a storage device storing the voltage signal detected at the time of each pulse; and
an oscillator generating the periodic signal whose frequency is controlled based on the voltage signal stored in the storage device.
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Accused Products
Abstract
A PLL circuit includes a sampling pulse generator and a loop circuit using a sample and hold circuit as a phase detector. The sampling pulse generator generates a sampling pulse signal at each level transition of an NRZ input signal. The sample and hold circuit samples a clock signal and hold a voltage signal corresponding to a voltage of the clock signal according to the sampling pulse signal. A voltage-controlled oscillator included in the loop circuit generates the clock signal whose frequency is controlled based on tho voltage signal received from the sample and hold circuit through a loop filter. The voltage signal remains at an appropriate level even when the NRZ input signal remains at the same level for a relatively long time. The sampling pulse generator includes a delay circuit for delaying the NRZ input signal and an exclusive-OR circuit receiving the NRZ input signal and the delayed signal.
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Citations
19 Claims
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1. A circuit comprising:
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a pulse generator generating a pulse signal of a predetermined pulse width at each level transition of an input signal having an NRZ (non return to zero) signaling method; a detector detecting a voltage signal corresponding to a voltage of a periodic signal at a time corresponding to each pulse of the pulse signal; a storage device storing the voltage signal detected at the time of each pulse; and an oscillator generating the periodic signal whose frequency is controlled based on the voltage signal stored in the storage device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A clock recovery circuit comprising:
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a sampling pulse generator for generating a sampling pulse signal of a predetermined pulse width at each level transition of an input signal having an NRZ (non return to zero) signaling method; a sample and hold circuit for sampling a clock signal according to the sampling pulse signal and holding a voltage signal corresponding to a voltage of the clock signal at the time corresponding to the sampling pulse signal; a filter receiving the voltage signal and producing a controlling signal; and a controlled oscillator for generating the clock signal whose frequency is controlled according to the controlling signal received from the filter. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A phase-locked loop circuit comprising:
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a phase detector for detecting and storing a voltage signal corresponding to a voltage of a periodic signal at each level transition of an input signal having an NRZ (non return to zero) signaling method; a loop filter receiving the voltage signal from the phase detector and producing a voltage controlling signal; and a voltage-controlled oscillator for generating the periodic signal whose frequency is controlled according to the voltage controlling signal received from tho loop filter. - View Dependent Claims (17)
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18. A method for recovering a clock signal from an input signal having an NRZ (non return to zero) signaling method, the method comprising the steps of:
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generating a pulse signal of a predetermined pulse width at each level transition of the input signal; detecting a voltage signal corresponding to a voltage of a periodic signal at a time corresponding to each pulse of the pulse signals; storing the voltage signal detected at the time of each pulse; and generating the periodic signal whose frequency is controlled based on the voltage signal. - View Dependent Claims (19)
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Specification