Method of analyzing failure of semiconductor device by using emission microscope and system for analyzing failure of semiconductor device

• US 5,760,892 A
• Filed: 12/17/1996
• Issued: 06/02/1998
• Est. Priority Date: 06/14/1996
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Koyama, Tohru
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Ratliff, Reginald A.
• Application Number:
  US08/767,640
• Time in Patent Office: 532 Days
• Field of Search: 356/237, 356/71, 356/429, 356/388, 356/390
• US Class Current: 356/237.1
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence
• CPC Class Codes: H01L 2223/5448 Located on chip prior to dicing and remaining on chip after dicing

Abstract

A method of analyzing a failure of semiconductor device by using an emission microscope for easy analysis of current leakage is disclosed. Light emission information is stored in X/Y memory spaces (16), with a Z direction indicating an emitted light intensity. A light emission presence bit (17) in the light emission information means a bit for which light emission is judged as being present, and the number of light emission presence bits is determined on the basis of the emitted light intensity. An image memory (11) has a three-dimensional memory space including an X/Y space indicative of plane positions of light emitting portions and a Z space indicative of the emitted light intensity. The position and intensity of light emission are detected by searching the light emission information stored in the image memory (11) to analyze the failure.

Claims

1. A method of analyzing a failure of a semiconductor device, comprising:

forming an emission image of said semiconductor device using an emission microscope, said emission image having light emitting portions at positions in the emission image relating to the two-dimensional position of corresponding positions on the semiconductor device;

storing light emission information in an image memory, said light emission information including data indicating the two-dimensional position of each of said light emitting portions on said emission image and emitted light intensity data associated with each of said light emitting portions on said emission image at each of the two-dimensional positions;

accessing said image memory to identify and retrieve said light emission information; and

analyzing a failure of said semiconductor device in the form of a numerical value on the basis of said retrieved light emission information.

2. The method of claim 1, wherein said step of accessing said image memory includes searching and scanning individual predetermined unit scanning areas in said image memory to detect any stored two-dimensional position data and related intensity data of stored light emitting portions.

3. A method of claim 1, wherein said step of accessing said image memory includes searching and scanning stored emitted light intensity data in said image memory in descending order of emitted light intensity relative to a predetermined emitted light intensity to access said two-dimensional position and intensity data relative to any of the stored light emitting portions.

4. A method of claim 1, wherein said semiconductor device includes a plurality of semiconductor devices each of said semiconductor devices having surfaces of the same configuration, and

wherein said step of analyzing a failure further includes,

accumulating light emissions data relative to each of said plurality of semiconductor devices on the basis of said light emission information to produce a frequency map for displaying a frequency distribution of light emitting portions having not less than a predetermined emitted light intensity relative to each of said surfaces, and

analyzing a failure of said plurality of semiconductor devices on the basis of said frequency map.

5. The method of claim 1, wherein said semiconductor device includes a plurality of semiconductor devices formed on a wafer, and said forming an emission image step includes,

forming emission microscope images of said plurality of semiconductor devices formed on said wafer and providing an identification of the positions of said plurality of semiconductor devices on said wafer, and

wherein said step of analyzing a failure further includes,

producing a light emission wafer map for collectively indicating light portions of each of said plurality of semiconductor devices on said wafer on the basis of said light emission information, and

analyzing a failure of said plurality of semiconductor devices on the basis of said light emission wafer map.

6. The method of claim 5, wherein said step of analyzing a failure of said plurality of said semiconductor devices further includes,

producing a plurality of defect wafer maps for collectively indicating defects in respective manufacturing processes associated with said wafer, and

comparing said light emission wafer map with said plurality of defect wafer maps to analyze a failure of said plurality of semiconductor devices.

7. The method of claim 5, wherein said plurality of semiconductor devices include a plurality of semiconductor memories, and

wherein said step of analyzing a failure of said plurality of semiconductor devices includes,

producing a fail bit map for collectively indicating failed bits of said plurality of semiconductor memories on said wafer, and

comparing said light emission wafer map with said fail bit map to analyze a failure of said plurality of semiconductor memories.

8. A method of analyzing a failure of a plurality semiconductor devices on a wafer by using an emission microscope, said method comprising the steps of:

producing a light emission wafer map for collectively indicating light emissions detected relative to the plurality of semiconductor devices formed on the wafer using said emission microscope;

producing defect wafer maps collectively indicating defects relative to respective manufacturing processes used to produce the plurality of semiconductor devices on said wafer, said plurality of semiconductor devices including a plurality of semiconductor memories;

producing a fail bit map collectively indicating failed bits of said plurality of semiconductor memories on said wafer; and

performing data management of said light emission wafer map, said defect wafer maps, and said fail bit map including verification of two of said light emission wafer map, said defect wafer maps, and said fail bit map by comparing the two with each other using a network interconnection so as to analyze a failure of said plurality of semiconductor devices.

9. A system for analyzing a failure of a semiconductor device on a wafer, comprising:

an analysis device having an emission microscope, said analysis device outputting a light emission wafer map collectively indicating light emissions of a plurality of semiconductor devices formed on the wafer using said emission microscope;

a defect check device outputting defect wafer maps collectively indicating defects in respective manufacturing processes relative to the plurality of semiconductor devices on said predetermined wafer;

said plurality of semiconductor devices including a plurality of semiconductor memories;

a tester outputting a fail bit map collectively indicating failed bits of said plurality of semiconductor memories on said wafer;

a computer performing data management of said light emission wafer map, said defect wafer maps, and said fail bit map including verification of two of said light emission wafer map, said defect wafer maps, and said fail bit map by comparing the two with each other and

wherein said emission microscope, said analysis device, said defect check device, said tester and said computer are connected together in a network.