Cost reduced interpolated timing recovery in a sampled amplitude read channel

• US 5,760,984 A
• Filed: 10/20/1995
• Issued: 06/02/1998
• Est. Priority Date: 10/20/1995
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Spurbeck, Mark S., Behrens, Richard T.
• Primary Examiner(s): Psitos, Aristotelis M.
• Assistant Examiner(s): WAMSLEY, PATRICK G
• Application Number:
  US08/546,162
• Time in Patent Office: 956 Days
• Field of Search: 360/51, 360/65, 360/40, 360/48, 371/43, 375/327, 375/340, 375/345, 375/354, 375/376, 348/416, 348/448, 348/628, 369/32, 369/59, 340/146.2, 331/25, 364/602, 364/724.1, 364/825, 341/59, 370/290, 380/49
• US Class Current: 360/51
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals
• CPC Class Codes: G11B 20/10037 A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
• CPC Class Codes: G11B 20/10055 using partial response filtering when writing the signal to the medium or reading it therefrom
• CPC Class Codes: G11B 20/10064 EEPR4 or E2PR4, i.e. extended partial response class 4, polynomial (1-D)*(1+D)3
• CPC Class Codes: G11B 20/10074 EPR4, i.e. extended partial response class 4, polynomial (1-D) *(1+D)2
• CPC Class Codes: G11B 20/1258 where blocks are arranged within multiple radial zones, e.g. Zone Bit Recording or Constant Density Recording discs, MCAV discs, MCLV discs
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: G11B 2020/1234 wherein the sector is a headerless sector, i.e. it does not comprise an ID field
• CPC Class Codes: H04L 2007/047 using a sine signal or unmodulated carrier
• CPC Class Codes: H04L 7/0029 interpolation of received data signal

Abstract

A sampled amplitude read channel reads information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium. A write VFO generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, the write VFO generates a sampling clock at a frequency slightly higher than the write frequency. A sampling device samples the analog read signal at the sampling clock rate to generate a sequence of discrete time channel samples that are not synchronized to the baud rate, and the channel samples are equalized by a discrete time equalizing filter according to a predetermined partial response (PR4, EPR4, EEPR4, etc.). An interpolating timing recovery circuit, responsive to the equalized channel samples, computes an interpolation interval τ and, in response thereto, generates interpolated sample values substantially synchronized to the baud rate. The timing recovery circuit also generates a data clock for clocking a discrete time sequence detector which detects the digital data from the interpolated sample values. In a cost reduced implementation, the interpolation filter coefficients are computed in real time as a function of the interpolation interval τ.

Claims

1. A sampled amplitude read channel for reading information stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values, the interpolated sample values generated by interpolating a sequence of discrete time channel sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic medium, the sampled amplitude read channel comprising:

(a) a sampling clock;

(b) a sampling device, responsive to the sampling clock, for sampling the analog read signal to generate the channel sample values;

(c) an interpolated timing recovery circuit, responsive to the channel sample values and an interpolation interval τ

, for generating the interpolated sample values using an interpolation filter having an actual impulse response h(n) comprised of a number of actual coefficients computed in real time as a function of τ and

a matrix of predetermined values G_i (n), wherein;

i equals 1 to L where L determines a degree that the actual coefficients approximate ideal coefficients;

n equals 1 to N where N is the number of actual coefficients in the actual impulse response h(n);

the ideal coefficients are represented by a matrix A;

the function of τ

is a lookup table into a matrix F; and

the matrix F is a factor of a rank reduced approximation of matrix A; and

(d) a discrete time detector for detecting the digital data from the interpolated sample values.

2. The sampled amplitude read channel as recited in claim 1, wherein an output Y(x) of the interpolation filter is generated according to:

##EQU19## U(x) are the discrete time channel sample values; and

f(i,τ

) is the function of τ

.

3. The sampled amplitude read channel as recited in claim 1, wherein an output Y(x) of the interpolation filter is generated according to:

##EQU20## U(x) are the discrete time channel sample values; and

f(i,τ

) is the function of τ

.

4. The sampled amplitude read channel as recited in claim 3, wherein:

(a) the ideal coefficients are represented by a matrix A;

(b) the function of τ

is a lookup table into a matrix F; and

(c) the matrix F and the matrix G_i (n) are factors of a rank reduced approximation of matrix A.

5. The sampled amplitude read channel as recited in claim 3, wherein ##EQU21## is implemented as a bank of discrete time FIR filters.

6. The sampled amplitude read channel as recited in claim 5, wherein:

(a) the ideal coefficients are represented by a matrix A;

(b) the function of τ

is a lookup table into a matrix F; and

(c) the matrix F and the matrix G_i (n) are factors of a rank reduced approximation of matrix A.

7. The sampled amplitude read channel as recited in claim 1, wherein the interpolated timing recovery further generates a data clock for clocking the discrete time detector.

8. The sampled amplitude read channel as recited in claim 7, wherein:

(a) the analog read signal comprises pulses modulated by the digital data at a predetermined baud rate; and

(b) a frequency of the data clock substantially matches the baud rate on average.

9. The sampled amplitude read channel as recited in claim 8, wherein the sampling clock cycles at a rate higher than the baud rate.

10. The sampled amplitude read channel as recited in claim 8, wherein the interpolated timing recovery comprises an AND gate responsive to the sampling clock and a mask signal, having an output for outputting the data clock, wherein the mask signal selectively masks sampling clock cycles such that the frequency of the data clock substantially matches the baud rate on average.

11. The sampled amplitude read channel as recited in claim 1, wherein:

(a) the analog read signal comprises pulses modulated by the digital data at a predetermined baud rate; and

(b) a magnitude of the interpolated sample values substantially matches a corresponding magnitude of the analog read signal at discrete times synchronous with the baud rate.

12. The sampled amplitude read channel as recited in claim 1, further comprising an equalizing filter for filtering the channel sample values according to a partial response selected from the group consisting of PR4, EPR4 and EEPR4.

13. The sampled amplitude read channel as recited in claim 1, wherein the analog read signal comprises pulses modulated by the digital data at a predetermined baud rate, the interpolated timing recovery further comprising:

(a) a frequency offset generator for generating a frequency offset Δ

f proportional to a frequency difference between the sampling clock and the baud rate; and

(b) a mod-Ts accumulator for accumulating, modulo-Ts, the frequency offset Δ

f to generate the interpolation interval τ

where Ts is a predetermined sample period.

14. The sampled amplitude read channel as recited in claim 13, wherein the frequency offset generator comprises:

(a) a phase error detector for detecting a phase error Δ

θ

between an interpolated sample value and an estimated sample value; and

(b) a loop filter for filtering the phase error Δ

θ

to generate the frequency offset Δ

f.

15. The sampled amplitude read channel as recited in claim 14, wherein the loop filter is a PID filter.

16. The sampled amplitude read channel as recited in claim 14, wherein:

(e) the mod-Ts accumulator outputs a mask pulse each time a dividend result, proportional to the accumulated frequency offset Δ

f integer divided by Ts, increments by 1; and

(f) the mask signal is used to generate a data clock for clocking the discrete time detector.

17. The sampled amplitude read channel as recited in claim 1, wherein the actual impulse response h(n) approximates an ideal impulse response,

18. The sampled amplitude read channel as recited in claim 17, wherein the actual impulse response h(n) is generated by minimizing:

##EQU22## C.sub.τ

(e^jω

) is the frequency response corresponding to the actual impulse response h(n);

e^jω

τ

is the frequency response corresponding to the ideal impulse response;

α

is a fractional value where 0<

α

≦

1; and

X(e^jω

) is a frequency response of the read channel.

19. The sampled amplitude read channel as recited in claim 18, wherein X(e^jω

) is selected from the group consisting of PR4, EPR4 and EEPR4.

20. The sampled amplitude read channel as recited in claim 1, wherein the interpolated timing recovery further comprises:

(a) a means for computing an interpolation interval τ

proportional to a time difference between a channel sample value and a desired interpolated sample value; and

(b) a zero phase start circuit comprising a means for computing an initial interpolation interval τ

.