Method and apparatus for modeling capacitance in an integrated circuit

• US 5,761,080 A
• Filed: 11/22/1995
• Issued: 06/02/1998
• Est. Priority Date: 11/22/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: DeCamp, William F., Habitz, Peter A., Ellis-Monaghan, John J., Seibert, Edward W.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): FREJD, RUSSELL WARREN
• Application Number:
  US08/561,647
• Time in Patent Office: 923 Days
• Field of Search: 395/500, 364/488-491, 364/578
• US Class Current: 716/115
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

According to the present embodiment, a method for calculating the parasitic capacitance in a semiconductor device is disclosed. According to the preferred method, a layout file containing the shapes of a semiconductor device is provided. The dimensions of the layout file are then adjusted to wafer dimensions so as reflect actual production devices. The shapes of the layout file are then partitioned into simpler shapes, typically abutted rectangles, called tiles. Each tile is then decomposed into overlap and fringe capacitance components, each component having a uniform capacitance environment with respect to its capacitance elements. The parasitic capacitance of the semiconductor device can thus be accurately computed, with an efficient use of resources. Additionally the preferred embodiment is easily adaptable to a wide range of technology types.

Claims

1. A computer apparatus comprising:

(a) a central processing unit;

(b) a memory, said memory accessible by said central processing unit, said memory containing an executable program;

wherein said program comprises;

i) a shape file input mechanism, wherein said input mechanism is adapted for inputting a shape file containing layout shapes of a semiconductor device, said layout shapes partitioned into a plurality of tiles;

ii) a decomposer, wherein said decomposer is adapted for decomposing said tiles of said shapes into a plurality of parasitic capacitance components, said plurality of parasitic capacitance components including fringe capacitance components having substantially uniform parasitic capacitance with regard to fringe capacitance and overlap capacitance components having substantially uniform parasitic capacitance with regard to overlap capacitance; and

iii) a parasitic capacitance calculator, wherein said parasitic capacitance calculator is adapted for computing parasitic capacitance of each of said plurality of tiles, said parasitic capacitance computation including calculation of the capacitance of each of said plurality of parasitic capacitance components.

2. The computer apparatus of claim 1 wherein said overlap capacitance components include a plurality of overlap-up components and a plurality of overlap-down components and wherein said fringe capacitance components include a plurality of first edge fringe components, and a plurality of second edge fringe components.

3. The computer apparatus of claim 2 wherein said plurality of overlap-up capacitance components and said plurality of overlap-down capacitance components each have uniform parasitic capacitance environments within a predetermined tolerance with respect to overlap capacitance and wherein said plurality of first edge fringe components and said plurality of second edge fringe components each have a uniform parasitic capacitance environment within a predetermined tolerance with respect to fringe-up capacitance, fringe-down capacitance, and fringe line-to-line capacitance.

4. The computer apparatus of claim 1 wherein said parasitic capacitance calculator is adapted for calculating overlap capacitance of said overlap capacitance components, and for calculating fringe-up capacitance, fringe-down capacitance, and fringe line-to-line capacitance.

5. The computer apparatus of claim 1 wherein said decomposer is adapted to decompose said tiles of said shapes into a plurality of parasitic capacitance components by:

i) decomposing said pluralities of tiles into said overlap capacitance components by recursively intersecting said tiles with shapes above and below said tile in said semiconductor device; and

ii) decomposing said plurality of tiles into said fringe capacitance components by intersecting edges of each of said plurality of tiles with adjacent shapes and then further partitioning for shapes above and below said edges.

6. The computer apparatus of claim 1 wherein said layout shape file includes a wafer dimension shape file.

7. The computer apparatus of claim 6 wherein said wafer dimension shape file is created from a shape file and said technology data file.

8. The computer apparatus of claim 7 wherein said technology data file comprises an executable file programed to adjust dimensions of the shape file to wafer dimensions corresponding to said technology data.

9. The computer apparatus of claim 1 wherein said tiles comprise rectangles.

10. The computer apparatus of claim 1 wherein said tiles comprise trapezoids.

11. A computer apparatus for calculating a parasitic capacitance of a semiconductor device comprising:

(a) a central processing unit;

(b) a memory, said memory accessible by said central processing unit, said memory containing an executable program;

wherein said program includes;

i) a layout file input mechanism, wherein said layout file input mechanism is adapted for inputting a layout file, said layout file containing shapes of a semiconductor device;

ii) a technology file input mechanism, wherein said technology file input mechanism is adapted for a inputting a technology file, said technology file adapted for adjusting dimensions of said shapes of said semiconductor device in said layout file to wafer dimensions;

iii) a partitioner, wherein said partitioner is adapted for partitioning said shapes of said semiconductor device into a plurality of tiles, said tiles each including a portion of a semiconductor shape;

iv) a decomposer, wherein said decomposer is adapted for decomposing said plurality of tiles of each of said plurality of shapes into a plurality of parasitic capacitance components, said plurality of parasitic capacitance components including overlap capacitance components having substantially uniform parasitic capacitance with regard to overlap capacitance and fringe capacitance components having substantially uniform parasitic capacitance with regard to fringe capacitance; and

v) a parasitic capacitance calculator, wherein said parasitic capacitance calculator is adapted for computing capacitance of said semiconductor device by computing said plurality of parasitic capacitance components.

12. The computer apparatus of claim 11 wherein said overlap capacitance components include a plurality of overlap-up components and a plurality of overlap-down components and wherein said fringe capacitance components include a plurality of first edge fringe components, and a plurality of second edge fringe components.

13. The computer apparatus of claim 12 wherein said plurality of overlap-up capacitance components and said plurality of overlap-down capacitance components each have uniform parasitic capacitance environments within a predetermined tolerance with respect to overlap capacitance and wherein said plurality of first edge fringe components and said plurality of second edge fringe components each have a uniform parasitic capacitance environment within a predetermined tolerance with respect to fringe-up capacitance, fringe-down capacitance, and fringe line-to-line capacitance.

14. The computer apparatus of claim 11 wherein said parasitic capacitance calculator is adapted for calculating overlap capacitance of said overlap capacitance components, and for calculating fringe-up capacitance, fringe-down capacitance, and fringe line-to-line capacitance.

15. The computer apparatus of claim 11 wherein said decomposer is adapted to decompose said tiles of said shapes into a plurality of parasitic capacitance components by:

i) decomposing said pluralities of tiles into said overlap capacitance components by recursively intersecting said tiles with shapes above and below said tile in said semiconductor device; and

ii) decomposing said plurality of tiles into said fringe capacitance components by intersecting edges of each of said plurality of tiles with adjacent shapes and then further partitioning for shapes above and below said edges.

16. The computer apparatus of claim 11 wherein said tiles comprise rectangles.

17. The computer apparatus of claim 11 wherein said shapes partitioned into a plurality of tiles are stored in a data base having a quad tree data structure.

18. A program product comprising:

a) a recordable media; and

b) a program recorded on said recordable media, the program used to calculate the parasitic capacitance of a semiconductor device, the program including;

i) a shape file input mechanism, wherein said input mechanism is adapted for inputting a shape file containing layout shapes of a semiconductor device, said layout shapes partitioned into a plurality of tiles;

ii) a decomposer, wherein said decomposer is adapted for decomposing said tiles of said shapes into a plurality of parasitic capacitance components, said plurality of parasitic capacitance components including fringe capacitance components having substantially uniform parasitic capacitance with regard to fringe capacitance and overlap capacitance components having substantially uniform parasitic capacitance with regard to overlap capacitance; and

iii) a parasitic capacitance calculator, wherein said parasitic capacitance calculator is adapted for computing parasitic capacitance of each of said plurality of tiles, said parasitic capacitance computation including calculation of the capacitance of each of said plurality of parasitic capacitance components.

19. The program product of claim 18 wherein said overlap capacitance components include a plurality of overlap-up components and a plurality of overlap-down components and wherein said fringe capacitance components include a plurality of first edge fringe components, and a plurality of second edge fringe components.

20. The program product of claim 19 wherein said plurality of overlap-up capacitance components and said plurality of overlap-down capacitance components each have uniform parasitic capacitance environments within a predetermined tolerance with respect to overlap capacitance and wherein said plurality of first edge fringe components and said plurality of second edge fringe components each have a uniform parasitic capacitance environment within a predetermined tolerance with respect to fringe-up capacitance, fringe-down capacitance, and fringe line-to-line capacitance.

21. The program product of claim 18 wherein said parasitic capacitance calculator is adapted for calculating overlap capacitance of said overlap capacitance components, and for calculating fringe-up capacitance, fringe-down capacitance, and fringe line-to-line capacitance.

22. The program product of claim 18 wherein said decomposer is adapted to decompose said tiles of said shapes into a plurality of parasitic capacitance components by:

i) decomposing said pluralities of tiles into said overlap capacitance components by recursively intersecting said tiles with shapes above and below said tile in said semiconductor device; and

ii) decomposing said plurality of tiles into said fringe capacitance components by intersecting edges of each of said plurality of tiles with adjacent shapes and then further partitioning for shapes above and below said edges.

23. A method for calculating parasitic capacitance in semiconductor circuit design, comprising the steps of:

a) inputting a shape file, said shape file containing layout shapes of a semiconductor device;

b) decomposing said shapes into a plurality of parasitic capacitance components, said plurality of parasitic capacitance components including fringe capacitance components having substantially uniform parasitic capacitance with regard to fringe capacitance and overlap capacitance components having substantially uniform parasitic capacitance with regard to overlap capacitance; and

c) computing parasitic capacitance of said semiconductor device, said computation including calculating the capacitance of each of said plurality of parasitic capacitance components.

24. The method of claim 23 wherein said overlap capacitance components include a plurality of overlap-up components and a plurality of overlap-down components and wherein said fringe capacitance components include a plurality of first edge fringe components, and a plurality of second edge fringe components.

25. The method of claim 24 wherein said plurality of overlap-up capacitance components and said plurality of overlap-down capacitance components each have uniform parasitic capacitance environments within a predetermined tolerance with respect to overlap capacitance and wherein said plurality of first edge fringe components and said plurality of second edge fringe components each have a uniform parasitic capacitance environment within a predetermined tolerance with respect to fringe-up capacitance, fringe-down capacitance, and fringe line-to-line capacitance.

26. The method of claim 23 wherein said parasitic capacitance is calculated by calculating overlap capacitance of said overlap capacitance components and by calculating fringe-up capacitance, fringe-down capacitance, and fringe line-to-line capacitance.

27. The method of claim 23 wherein said shapes are partitioned into tiles and wherein said step of decomposing shapes into plurality of capacitance components comprises decomposing said tiles of said shapes into a plurality of parasitic capacitance components by:

i) decomposing said pluralities of tiles into said overlap capacitance components by recursively intersecting said tiles with shapes above and below said tile in said semiconductor device; and

ii) decomposing said plurality of tiles into said fringe capacitance components by intersecting edges of each of said plurality of tiles with adjacent shapes and then further partitioning for shapes above and below said edges.

28. The method of claim 23 wherein said fringe capacitance components comprise are fringe-up, fringe-down, and fringe line-to-line capacitances, said capacitances partitioned using partitioning angles, said partitioning angles defined as:

##EQU15##

29. The method of claim 23 wherein said step of computing said parasitic capacitance comprises computing an overlap-up, overlap-down and said fringe capacitance component, wherein:

i) said overlap-up and overlap-down capacitance components are computed, where C_overlap is the overlap capacitance, according to,

space="preserve" listing-type="equation">C.sub.overlap =C.sub.a (W-2b'"'"'t) (fF/μ

m) (22)

ii) said fringe capacitance component is calculated by computing a fringe-up, fringe-down, and fringe line-to-line capacitance element, and where said fringe-up capacitance, C_fringe-up, is calculated according to, ##EQU16## wherein said fringe-down capacitance, C_fringe-down, is calculated according to, ##EQU17## and where said fringe line-to-line capacitance, C_line-to-line, is calculated according to, ##EQU18##

30. The method of claim 23 wherein said layout shape file comprises a wafer dimension shape file.

31. The method of claim 23 wherein a wafer dimension shape file is created from a shape file and said technology data file.

32. The method of claim 23 wherein said shapes are partitioned into tiles and wherein said tiles comprise abutted rectangles.

33. The method of claim 23 wherein said shapes are partitioned into tiles and wherein said tiles comprise trapezoids.

34. A computer implemented method for calculating the parasitic capacitance in a semiconductor design, comprising the steps of:

a) inputting a layout file, said layout file containing shapes of a semiconductor device;

b) inputting a technology file, said technology file adapted to adjust said shapes of said semiconductor device in said layout file to wafer dimensions;

c) partitioning said shapes of said semiconductor device into a plurality of tiles, said tiles each including a portion of a semiconductor shape;

d) decomposing said plurality of tiles of each of said plurality of shapes into a plurality of parasitic capacitance components, said plurality of parasitic capacitance components including overlap capacitance components having substantially uniform parasitic capacitance with regard to overlap capacitance and fringe capacitance components having substantially uniform parasitic capacitance with regard to fringe capacitance; and

e) computing capacitance of said semiconductor device by computing capacitance of said plurality of parasitic capacitance components.

35. The method of claim 34 wherein said overlap capacitance components include a plurality of overlap-up components and a plurality of overlap-down components and wherein said fringe capacitance components include a plurality of first edge fringe components, and a plurality of second edge fringe components.

36. The method of claim 35 wherein said plurality of overlap-up capacitance components and said plurality of overlap-down capacitance components each have uniform parasitic capacitance environments within a predetermined tolerance with respect to overlap capacitance and wherein said plurality of first edge fringe components and said plurality of second edge fringe components each have a uniform parasitic capacitance environment within a predetermined tolerance with respect to fringe-up capacitance, fringe-down capacitance, and fringe line-to-line capacitance.

37. The method of claim 34 wherein said parasitic capacitance is calculated by calculating overlap capacitance of said overlap capacitance components and by calculating fringe-up capacitance, fringe-down capacitance, and fringe line-to-line capacitance.

38. The method of claim 34 wherein said shapes are partitioned into tiles and wherein said step of decomposing shapes into plurality of capacitance components comprises decomposing said tiles of said shapes into a plurality of parasitic capacitance components by:

i) decomposing said pluralities of tiles into said overlap capacitance components by recursively intersecting said tiles with shapes above and below said tile in said semiconductor device; and

ii) decomposing said plurality of tiles into said fringe capacitance components by intersecting edges of each of said plurality of tiles with adjacent shapes and then further partitioning for shapes above and below said edges.

39. The method of claim 34 wherein the step of partitioning said shapes into a plurality of tiles further comprises storing said shapes and said tiles of said shapes in a data base.

40. The method of claim 39 wherein said data base comprises a quad-tree data structure.

41. A computer implemented method for calculating the parasitic capacitance in a semiconductor design, comprising the steps of:

a) inputting a layout file, said layout file containing shapes of a semiconductor device;

b) inputting a technology file, said technology file an executable file adapted to adjust said shapes of said semiconductor device in said layout file to wafer dimensions;

c) partitioning said shapes of said semiconductor device into a plurality of butted rectangle tiles, said tiles each including a portion of a semiconductor shape;

d) storing said wafer dimension layout shapes, said tiles of said shapes in a quad-data base

e) creating a netlist data base;

f) decomposing said plurality of tiles of said plurality of shapes into a plurality overlap-up and overlap-down parasitic capacitance components,

g) decomposing edges of said plurality of tiles of said plurality of shapes into a plurality of fringe capacitance components, each of said fringe capacitance components having a uniform parasitic capacitance environment with respect to fringe-up, fringe-down, and fringe line-to-line capacitance;

h) creating a geometry file, said geometry file containing wafer geometry dimensions corresponding to said parasitic capacitance components; and

i) computing capacitance of said semiconductor device, said computing done by computing plurality of parasitic capacitance components using said wafer dimension geometry file.