Memory cell capable of storing more than two logic states by using programmable resistances

• US 5,761,110 A
• Filed: 12/23/1996
• Issued: 06/02/1998
• Est. Priority Date: 12/23/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Kapoor, Ashok, Wik, Thomas R., Irrinki, V. Swamy, Owens, Alex, Leung, Raymond T.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Tran, Andrew Q.
• Application Number:
  US08/779,992
• Time in Patent Office: 526 Days
• Field of Search: 365/100, 365/96, 365/104, 365/148, 365/163, 365/168, 365/189.07, 257/390, 257/379
• US Class Current: 365/100
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency

Abstract

A system and process which enables storage of more than two logic states in a memory cell. In one embodiment, a programmable resistor is coupled in series with a transistor between a supply voltage and a data read line. When an access signal is asserted, the transistor provides a conductive path, and a voltage drop is sustained by the programmable resistor. The programmable resistor has a resistance which is set during a programming step to one of a plurality of values by passing a heating current through the programmable resistor for one of a corresponding plurality of predetermined lengths of time. When the access signal is asserted, the voltage drop sustained across the programmable resistor is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

Claims

1. A programmable resistor of a memory circuit comprising a mixture of titanium and oxygen coupled to conduct a heating current, wherein at least a portion of said mixture is configured to reach a temperature near 450°

C. while said heating current is present, and wherein said mixture is configured to at least partially transform to TiO₂.

2. The programmable resistor of claim 1, wherein said mixture is coupled to conduct a sense current, and wherein said mixture is configured to sustain a voltage drop.

3. The programmable resistor of claim 2, wherein said mixture is configured to have the voltage drop set to a desired value by conducting said heating current for a predetermined length of time.

4. The programmable resistor of claim 2, wherein said mixture is configured to have the voltage drop set to one of at least three distinct digital values by conducting said heating current for a predetermined length of time.

5. The programmable resistor of claim 1, wherein said mixture is a film deposited on an insulating dielectric layer.

6. The programmable resistor of claim 5, wherein said mixture connected to two metal contacts.

7. The programmable resistor of claim 5, wherein said insulating dielectric layer comprises SiO₂.

8. The programmable resistor of claim 6, wherein said metal contacts comprise an alloy of aluminum and copper.

9. A memory circuit comprising:

an access transistor having a gate, wherein said gate is coupled to receive an access signal, and wherein said access transistor is configured to provide a conductive path between a supply voltage and a data read line when said access signal is asserted;

a programmable resistor coupled between said supply voltage and said data read line in series with said access transistor, wherein said programmable resistor is configured to sustain a voltage drop when said access signal is asserted; and

an analog-to-digital converter coupled said data read line to detect a value indicative of said voltage drop, wherein said analog to digital converter is configured to convert said value to one of at least three distinct digital values.

10. The memory circuit of claim 9 wherein the programmable resistor has a resistance which is set to determine the voltage drop, said resistance is set to one of at least three magnitudes.

11. The memory circuit of claim 10, wherein the programmable resistor comprises two chemical reactants and a compound, wherein said reactants are configured to form said compound when heat is applied, and wherein said heat is applied for a predetermined length of time to said compound to set the resistance of said programmable resistor.

12. The memory circuit of claim 11, wherein said reactants are titanium and oxygen, and said compound is TiO₂.

13. The memory circuit of claim 11, wherein said heat is applied by passing a heating current through said programmable resistor.

14. The memory circuit of claim 9, wherein said analog-to-digital converter comprises a plurality of comparators, each coupled to compare an input voltage to one of a plurality of reference voltages.

15. The memory circuit of claim 9, further comprising an address decoder configured to assert said access signal in response to receiving an address signal and an enable signal.

16. The memory circuit of claim 9, further comprising a data gate configured to convert said distinct digital values into n binary data bits during a read operation.

17. The memory circuit of claim 9, further comprising a sense amplifier coupled to detect said voltage drop, said sense amplifier configured to responsively provide said value to said analog-to-digital converter.

18. A method for storing more than two logic states in a memory cell, comprising the steps of:

fabricating an array of access transistors each having a gate, wherein said gate is coupled to receive an access signal, and wherein each of said access transistors is configured to provide a conductive path between a supply voltage and a data read line when said access signal is asserted;

fabricating an array of programmable resistors, wherein each of said programmable resistors is coupled between said supply voltage and said data read line in series with a corresponding one of said access transistors, wherein each of said programmable resistor is configured to sustain a voltage drop when said access signal is asserted; and

applying a heating current to a first set of programmable resistors for a first predetermined length of time to cause said first set of programmable resistors to have a first resistance;

applying a heating current to a second set of programmable resistors for a second predetermined length of time to cause said second set of programmable resistors to have a second resistance; and

applying a heating current to a third set of programmable resistors for a third predetermined length of time to cause said third set of programmable resistors to have a third resistance.

19. The method of claim 18, further comprising the step of fabricating an analog-to-digital converter coupled to detect a value indicative of said voltage drop, wherein said analog to digital converter is configured to convert said value to one of at least three distinct digital values.

20. The method of claim 18, further comprising the step of fabricating an address decoder configured to assert said one of said access signals in response to receiving an address signal and an enable signal.