Cell threshold value distribution detection circuit and method of detecting cell threshold value

• US 5,761,125 A
• Filed: 08/09/1995
• Issued: 06/02/1998
• Est. Priority Date: 08/10/1994
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Himeno, Toshihiko
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/512,914
• Time in Patent Office: 1,028 Days
• Field of Search: 365/185.21, 365/185.01, 365/185.24
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

The features of the present invention are that the distribution of the threshold voltages of cell transistors in one row of a non-volatile memory cell array can be measured by the I-V characteristic measurement for one time. In the cell threshold distribution detection circuit, a plurality of voltage comparison circuits are provided respectively for the bit lines, each for comparing a voltage of a corresponding bit line with a reference voltage VREF. Each of the comparison circuits has a first current node for allowing a first current I1 to flow in the case where the bit line voltage is higher than the reference voltage, and a second current node for allowing a second current I2 to flow in the case where the bit line voltage is lower than the reference voltage. The first current nodes of the comparison circuits are commonly connected to an external pad and the second current nodes of the comparison circuits are commonly connected to an external pad.

Claims

1. A circuit for providing a cell threshold distribution output comprising:

a memory cell array, formed on a semiconductor substrate, in which cell transistors constituting non-volatile memory cells are arranged in rows and columns;

a plurality of word lines each connected to cell transistors of a corresponding row of said memory cell array and applied with a word line voltage for selecting the row;

a plurality of bit lines for transferring data from/to cell transistors of said memory cell array;

a plurality of bit line loads connected between said bit lines of said memory cell array and a first pad; and

a plurality of voltage comparison circuits each connected to a respective corresponding one of said bit lines, each voltage comparison circuit comparing a voltage of the corresponding bit line with a reference voltage each voltage comparison circuit having a first current node for allowing a first current to flow in the case where the bit line voltage of the corresponding bit line is higher than the reference voltage, and a second current node for allowing a second current to flow in the case where the bit line voltage of the corresponding bit line is lower than the reference voltage, the first current nodes of each of said voltage comparison circuits being connected to a second pad and the second current nodes of each of said voltage comparison circuits being connected to a third pad.

2. A circuit according to claim 1, wherein each of said plurality of voltage comparison circuits includes:

a first NMOS transistor, a first end of which is connected to said second pad and a gate of which is connected to the corresponding bit line;

a second NMOS transistor, a first end of which is connected to said third pad, a gate of which is connected to the reference voltage and a second end of which is connected to a second end of said first NMOS transistor; and

a constant current source connected to a node between said first and second NMOS transistors and a ground node.

3. A circuit according to claim 2, wherein said constant current source comprises an NMOS transistor, a gate of which is connected to a fourth pad and applied with a gate voltage via said fourth pad.

4. A circuit according to claim 2, wherein each of said bit line loads comprises an NMOS transistor.

5. A circuit according to claim 4, wherein a gate of each of said NMOS transistors comprising said bit line loads is connected to a fifth pad and applied with a gate voltage via said fifth pad.

6. A circuit according to claim 2, wherein a fourth pad is provided and applied with the reference voltage.

7. A method of providing a cell threshold distribution output applied to a circuit for providing a cell threshold distribution detection output comprising:

a memory cell array, formed on a semiconductor substrate, in which cell transistors constituting non-volatile memory cells are arranged in rows and columns;

a plurality of word lines each connected to cell transistors of a corresponding row of said memory cell array;

a plurality of bit lines for transferring data from/to cell transistors of said memory cell array;

a plurality of bit line loads connected between said bit lines of said memory cell array and a first pad; and

a plurality of voltage comparison circuits each connected to a respective corresponding one of said bit lines, each voltage comparison circuit comparing a voltage of the corresponding bit line with a reference voltage and each voltage comparison circuit having a first current node for allowing a first current to flow in the case where the bit line voltage of the corresponding bit line is higher than the reference voltage, and a second current node for allowing a second current to flow in the case where the bit line voltage of the corresponding bit line is lower than the reference voltage, the first current nodes of each of said voltage comparison circuits being connected to a second pad and the second current nodes of each of said voltage comparison circuits being connected to a third pad,

said method comprising the steps of;

applying voltages to the word lines of non-selected rows in said memory cell array so that all the memory cells connected to the word lines of the non-selected rows are turned off;

increasing a voltage of a word line of a selected row in said memory cell array from a voltage by which all the memory cells connected to the word line of the selected row are turned off to a voltage by which all the memory cells connected to the word line of the selected row are turned on; and

detecting a cell threshold distribution of the memory cells connected to the word line of the selected row by differentiating at least one of a current flowing in the second pad and a current flowing in the third pad, which change in accordance with a change in the voltage of the word line of the selected row.

8. A circuit for providing a cell threshold distribution output comprising:

a memory cell array, formed on a semiconductor substrate, in which a plurality of cell transistors constituting a plurality of non-volatile memory cells are arranged in rows and columns;

a plurality of word lines each connected to those of the cell transistors which are in a corresponding row in said memory cell array;

a plurality of bit lines for transferring data from/to the cell transistors of said memory cell array;

a plurality of voltage comparison circuits each connected to a respective corresponding one of said bit lines, each voltage comparison circuit having a first current node and a second current node and each voltage comparison circuit comparing a voltage of the corresponding bit line and a reference voltage to allow a first current to flow through said first current node in the case where the voltage of the corresponding bit line is higher than the reference voltage and a second current to flow through said second current node in the case where the voltage of the corresponding bit line is lower than the reference voltage;

a first pad connected to the first current nodes of each of said voltage comparison circuits;

a second pad connected to the second current nodes of each of said voltage comparison circuits; and

a plurality of third pads, each of said third pads connected to a respective corresponding one of said word lines.

9. A circuit according to claim 8, wherein each of said voltage comparison circuits includes:

a first NMOS transistor, a first end of which is connected to said first pad and a gate of which is connected to the corresponding bit line;

a second NMOS transistor, a first end of which is connected to said second pad, a gate of which is connected to the reference voltage and a second end of which is connected to a second end of said first NMOS transistor; and

a constant current source connected to a node between said first and second NMOS transistors and a ground node.

10. A circuit according to claim 9, wherein said constant current source includes an NMOS transistor, a gate of which is connected to a fourth pad applied with an external gate voltage.

11. A circuit according to claim 8, further including loads connected between a power supply and said bit lines, each load comprising an NMOS transistor.

12. A circuit according to claim 11, wherein the gates of the NMOS transistors comprising said loads are connected to a fifth pad applied with an external gate voltage.

13. A circuit according to claim 8, further including a fourth pad applied with the reference voltage.

14. A circuit for providing a cell threshold distribution output comprising:

a memory cell array, formed on a semiconductor substrate, in which a plurality of cell transistors constituting a plurality of non-volatile memory cells are arranged in rows and columns;

a plurality of word lines each connected to those of the cell transistors which are in a corresponding row in said memory cell array;

a plurality of bit lines for transferring data from/to the cell transistors of said memory cell array;

a plurality of operational amplifiers, each operational amplifier connected to a respective corresponding one of said bit lines, each operational amplifier comparing a voltage of the corresponding bit line and a reference voltage to output an output voltage having a first level in the case where the voltage of the corresponding bit line is higher than the reference voltage and a second level in the case where the voltage of the corresponding bit line is lower than the reference voltage;

a first pad;

a plurality of NMOS transistors, each NMOS transistor having a gate for receiving an output voltage of a respective corresponding one of said operational amplifiers and a first end connected to said first pad, each of the NMOS transistors being turned on when the output voltage of the corresponding operational amplifier has the first level to thereby allow a current through said first pad to flow; and

a plurality of second pads, each of said second pads connected to a respective corresponding one of said word lines.

15. A circuit according to claim 14, further including a plurality of current limiting NMOS transistors, each current limiting NMOS transistor being connected in series to one of said NMOS transistors.

16. A circuit according to claim 14, further including load connected between a power supply and said bit lines, each load comprising an NMOS transistor.

17. A circuit according to claim 16, wherein gates of the NMOS transistors comprising said loads are connected to a third pad applied with an external gate voltage.

18. A circuit according to claim 14, further including a third pad applied with the reference voltage.

19. A circuit for providing a cell threshold distribution output comprising:

a memory cell array, formed on a semiconductor substrate, in which a plurality of cell transistors constituting a plurality of non-volatile memory cells are arranged in rows and columns;

a plurality of word lines each connected to those of the cell transistors which are in a corresponding row in said memory cell array;

a plurality of bit lines for transferring data from/to the cell transistors of said memory cell array;

a plurality of operational amplifiers each connected to a respective corresponding one of said bit lines, each operational amplifier comparing a voltage of the corresponding bit line and a reference voltage to output an output voltage having a first level in the case where the voltage of the corresponding bit line is higher than the reference voltage and a second level in the case where the voltage of the corresponding bit line is lower than the reference voltage;

a first pad;

a plurality of NMOS transistors, each NMOS transistor having a gate for receiving an output voltage of a corresponding one of said operational amplifiers, a first end connected to said first pad, and a second end connected to ground, each of the NMOS transistors being turned on when the output voltage of the corresponding operational amplifier has the first level to allow a current through said first pad to flow; and

a plurality of second pads, each of said second pads connected to a respective corresponding one of said word lines.

20. A circuit for providing a cell threshold distribution output comprising:

a memory cell array, formed on a semiconductor substrate, in which cell transistors constituting non-volatile memory cells are arranged in rows and columns, said cell transistors arranged in NAND strings each comprising a plurality of said cell transistors and a selection-gate transistor connected in series;

a plurality of word lines each connected to those of the cell transistors which are in a corresponding row in said memory cell array;

a plurality of bit lines for transferring data from/to the cell transistors of said memory cell array;

a plurality of flip-flop circuits each connected to a respective corresponding one of said bit lines, each flip-flop circuit having a first data node and a second data node for latching complementary logic level data, the first data node being connected to said memory cell array;

a first pad;

a plurality of first NMOS transistors, each first NMOS transistor having a gate connected to the second data node of a corresponding flip-flop circuit, a first end connected to said first pad, and a second end connected to ground, each of said first NMOS transistors being turned on when a logic level data of the second date node of the corresponding flip-flop circuit changes from a first logic level to a second logic level to allow a current through said first pad to flow; and

a plurality of second pads, each of said second pads connected to a respective corresponding one of said word lines.

21. A circuit according to claim 20, further including loads connected between a power supply and said bit lines, said loads comprising PMOS transistors.

22. A circuit according to claim 21, wherein gates of the PMOS transistors comprising the loads are connected to a third pad applied with an external a gate voltage.

23. A circuit according to claim 20, further including a plurality of current limiting NMOS transistors, each current limiting NMOS transistor connected in series to one of said first NMOS transistors.

24. A circuit according to claim 20, further comprising a third pad connected to gates of said current limiting NMOS transistors.

25. A circuit according to claim 20, further comprising a data rewriting circuits each including second and third NMOS transistors connected in series between a power supply node and a corresponding bit line, a gate of the second NMOS transistor being connected to a third pad applied with a gate control signal and a gate of the third NMOS transistor being connected to the first data node of a corresponding flip-flop circuit, and a first transfer gate transistor connected between the corresponding bit line and the first data node of the corresponding flip-flop circuit, a second transfer gate transistor being connected between the second data node of the corresponding flip-flop circuit and the gate of a corresponding first NMOS transistor and a third transfer gate transistor connected between the first data node of the corresponding flip-flop circuit and the gate of the corresponding first NMOS transistor.

26. A circuit according to claim 20, further comprising a PMOS transistor for power supply, connected between a power supply and the drains of said first NMOS transistors.

27. A circuit according to claim 20, further comprising inverting circuits for inverting the data logic level of the second data terminal of said flip-flop circuits, each inverting circuit including second and third NMOS transistors connected in series between the second data node of a corresponding flip-flop circuit and the ground potential, a gate of the second NMOS transistor being connected to a corresponding bit line and a gate of the third NMOS transistor being connected to a third pad supplied with a gate control signal, first transfer gate transistors connected between said bit lines and the first data nodes of said flip-flop circuits, second transfer gate transistors connected between the second data nodes of said flip-flop circuits and the gates of said first transistors, and third transfer gate transistors connected between the first data nodes of said flip-flop circuits and the gates of said the first NMOS transistors.

28. A circuit for providing a cell threshold distribution output comprising:

a memory cell array, formed on a semiconductor substrate, in which a plurality of cell transistors constituting a plurality of non-volatile memory cells are arranged in rows and columns;

a plurality of voltage comparison circuits each connected to a respective corresponding one of said bit lines, each voltage comparison circuit comprising a plurality of rows extending in a first direction formed in the semiconductor substrate, each of the rows including first to sixth impurity regions of a conductivity type, a first conductive pattern extending in a second direction perpendicular to said first direction, a second conductive pattern extending in the second direction, and a plurality of third conductive patterns extending in the second direction, the first conductive pattern including a conductive layer extending over the rows and between first and second impurity regions, the second conductive pattern including first and second conductive layers connected at one ends thereof by a conductive layer extending in the first direction, extending over the rows and between the second impurity region and the third impurity region and between the third impurity region and the fourth impurity region, respectively, each of the third patterns including fourth and sixth conductive layers connected at one ends thereof by a conductive layer extending in the first direction, extending over a row and between the fourth impurity region and the fifth impurity region and between the fifth impurity region and the sixth impurity region, respectively, a first wiring layer for connecting the second impurity region, the fourth impurity region, and the sixth impurity region in a row, a second wiring layer for connecting the first impurity regions to a reference potential pad, a third wiring layer for connecting the third impurity regions to a first pad, a fourth wiring layer for connecting fifth impurity regions to a second pad, a fifth wiring layer for connecting the second conductive pattern to a third pad supplied with a reference potential;

a plurality of bit lines extending in the first direction, each connected to the third conductive pattern; and

a plurality of word lines extending in the second direction, each connected to those of the cell transistors which are in a corresponding row in said memory cell array.