Non-volatile semiconductor memory device

• US 5,761,128 A
• Filed: 03/26/1997
• Issued: 06/02/1998
• Est. Priority Date: 03/28/1996
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Watanabe, Kazuo
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/827,056
• Time in Patent Office: 433 Days
• Field of Search: 365/189.01, 365/201, 365/210
• US Class Current: 365/189.15
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 29/36 Data generation devices, e.g. data inverters
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/835 with roll call arrangements for redundant substitutions

Abstract

An EPROM has a main memory cell block, test memory cell block and a redundant memory cell block in a memory cell array. The test memory cell block stores a test pattern for a device test after fabrication and a signature code including a maker code and a device code. If some memory cell group in the main memory cell block are substituted for by memory cell group in the redundant memory cell block, the corresponding bit of the signature code is generated by a signature code generator in accordance with the data for the faulty group. The signature code generator selects data read from the redundant memory cell block or the generated bit of the signature code depending on the mode of the memory device.

Claims

1. A non-volatile semiconductor memory device comprising:

an array of non-volatile memory cells including a main memory cell block, a test memory cell block for storing a signature code, and a redundant memory cell block;

a signal read block including a first read section for reading data stored in the main memory cell block and the signature code stored in the test memory cell block, and a second read section for reading data stored in the redundant memory cell block;

a mode selector for selecting both a normal operation mode and a signature read mode of the memory device;

a signal generator including a substitute signal generator for generating a substitute signal indicating that a faulty memory cell group in the main memory cell block be substituted for by said redundant memory cell block, and a logic control signal generator for generating bits of the signature code based on the substitute signal during the signature read mode;

and a selecting block including a first selecting section for selecting one of an output from the first read section and an output from the second read section based on the substitute signal during the normal operation mode, and a second selecting section for selecting an output from said second read section or an output from the signature code generator dependently of the normal operation mode or signature code read mode.

2. A non-volatile semiconductor memory device as defined in claim 1, wherein the test memory cell block further stores a test pattern which is read during the normal operation mode by the first section.

3. A non-volatile semiconductor memory device as defined in claim 1, wherein the signature code includes a first code and a second code, and said logic control signal generator generates first signal and second signal for defining bits of first code and second code, respectively.

4. A non-volatile semiconductor memory device as defined in claim 1 wherein each of the memory cells in said test memory cell block stores said signature code by presence or absence of connection between a drain of the each of the memory cells and a corresponding bit line.