Data input/output circuit for performing high speed memory data read operation

• US 5,761,130 A
• Filed: 04/04/1997
• Issued: 06/02/1998
• Est. Priority Date: 07/06/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Quantum Devices Inc (Micron Technology, Inc.)
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US08/832,947
• Time in Patent Office: 424 Days
• Field of Search: 365/189.01, 365/189.02, 365/189.03, 365/189.05, 365/193, 365/189.04
• US Class Current: 365/189.16
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches
• CPC Class Codes: G11C 7/1093 Input synchronization

Abstract

A data input/output circuit used to program the cells of a memory array or to determine the state of those cells. The circuit includes a data write path used for programming the memory cells in the array and a data read path for reading data indicative of the state of the cells. The data write path includes switching means for electrically disconnecting the high capacitance elements of the write path from the read path. The switching means is under the control of a control means which acts to enable or disable the switching means. The switching means serves to electrically isolate the high capacitance elements of the write path from the read path, thereby increasing the speed with which a read operation be performed.

Claims

1. A flash memory system, comprising:

an array of flash memory cells;

a contact pad for providing an electrical interface between a flash memory cell in the array of flash memory cells and an operating environment;

a multiplexer for accessing a flash memory cell contained in the array of flash memory cells;

a data read path extending between the contact pad and the multiplexer for reading data from the accessed flash memory cell;

a data write path extending between the contact pad and the multiplexer for writing data to the accessed flash memory cell;

a data line electrically connected at a first end to the multiplexer and electrically connected at a second end to the accessed flash memory cell;

data writing means for generating a programming voltage for writing data to the accessed flash memory cell, wherein the data writing means is included in the data write path, and further, wherein the data writing means includes an element having a first capacitance value;

decoupling means electrically connected to the data write path and placed between the data writing means and the data line, the decoupling means including an element having a second capacitance value and being responsive to a control signal by electrically disconnecting the data writing means and the data line when not performing a data writing operation on the flash memory cell, thereby electrically disconnecting the element having the first capacitance value from the data line; and

control means for generating the control signal for the decoupling means.

2. The flash memory system of claim 1, wherein the data writing means includes a transistor operating in a source follower mode.

3. The flash memory system of claim 1, wherein the decoupling means includes an N-channel MOS device.

4. The flash memory system of claim 1, wherein the decoupling means serves as a pass device to pass the voltage and current generated by the data writing means when the decoupling means acts to electrically connect the data writing means and the data line.

5. The flash memory system of claim 1, wherein the second capacitance value is less than the first capacitance value.