Signal processing apparatus and method

• US 5,761,210 A
• Filed: 06/07/1995
• Issued: 06/02/1998
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Coases Investments Bros LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Claydon, Anthony Peter J., Gammack, Richard J.
• Primary Examiner(s): CHUNG, PHUNG M
• Application Number:
  US08/486,750
• Time in Patent Office: 1,091 Days
• Field of Search: 371/2.1, 371/38.1, 371/39.1, 371/37.5, 371/37.7, 375/340, 395/846, 395/166, 395/200.13, 395/421.07, 395/858, 395/475, 395/800, 395/467
• US Class Current: 714/701
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/151 using error location or error correction polynomials
• CPC Class Codes: H03M 13/2707 Simple row-column interleaver, i.e. pure block interleaving
• CPC Class Codes: H03M 13/2764 Circuits therefore
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 2027/0032 at baseband and passband
• CPC Class Codes: H04L 2027/0061 remodulation
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 2027/0073 Detection of synchronisation state
• CPC Class Codes: H04L 2027/0081 between loops of different bandwidths
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03866 using scrambling
• CPC Class Codes: H04L 25/062 Setting decision thresholds using feedforward techniques only
• CPC Class Codes: H04L 27/02 Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop
• CPC Class Codes: H04L 27/3809 Amplitude regulation arrangements
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/211 : Ghost signal cancellation H04N23/81 takes precedence
• CPC Class Codes: H04N 5/4446 : IF amplifier circuits specially adapted for B&W TV RF amplifiers in general H03F3/189
• CPC Class Codes: H04N 5/455 : Demodulation-circuits
• CPC Class Codes: H04N 5/52 : Automatic gain control

Abstract

An integrated CMOS circuit is disclosed for deinterleaving transmitted data packets. The circuit operates with a RAM buffer that is no larger than a block of interleaved data. An optimized addressing scheme is provided that minimizes on-chip hardware. The circuit provides an orderly initialization of the buffer, and a suitable emptying process during a channel change or other interruption of data flow.

Claims

1. A deinterleaving circuit for processing of a signal comprising blocks of interleaved data packets represented therein, comprising:

a random access memory for memorizing a data stream of said blocks of interleaved packets, wherein a capacity of said memory does not exceed any of said blocks;

a first circuit for generating an address signal representing a sequence of addresses of said random access memory, wherein successive addresses differ by an addressing interval;

a second circuit for successively reading and writing data out of and into said random access memory respectively at a reading address and a writing address of said random access memory, said reading address and said writing address being determined by said address signal, wherein said address signal is constant during an operation comprising reading and writing data at said address; and

a third circuit responsive to a signal ACCEPT BLOCK for periodically increasing said addressing interval by a value equal to an interleaving depth of said interleaved packets wherein said signal ACCEPT BLOCK is asserted after completion of an operation comprising a complete deinterleaving of one of said blocks of data.

2. The circuit according to claim 1, wherein said first circuit comprises a row predecoder.

3. The circuit according to claim 1, wherein said random access memory, said first circuit, said second circuit, and said third circuit are integrated in a semiconductor integrated circuit.

4. The circuit according to claim 1, further comprising a control means for second circuit, wherein said second circuit operates in a selected one of a first operating mode, wherein a writing operation is enabled and a reading operation is disabled;

a second operating mode, wherein said writing operation is enabled and said reading operation is enabled; and

a third operating mode, wherein said writing operation is disabled and said reading operation is enabled.

5. A deinterleaving circuit for processing of a signal having blocks of interleaved data packets represented therein, comprising:

a single, non-interleaved random access memory for memorizing said interleaved packets;

a first circuit for generating an address signal representing a sequence of addresses of said random access memory, wherein successive addresses differ by an addressing interval;

a second circuit for successively reading data of a first packet out of said random access memory and successively writing data of a second packet into said random access memory;

wherein said second circuit is responsive to said address signal; and

a third circuit responsive to a signal ACCEPT BLOCK for periodically increasing said addressing interval by a value equal to an interleaving depth of said interleaved packets wherein said signal ACCEPT BLOCK is asserted after completion of an operation comprising a complete deinterleaving of one of said blocks of data.

6. The circuit according to claim 5, wherein said random access memory, said first circuit, said second circuit, and said third circuit are integrated in a semiconductor integrated circuit.

7. The circuit according to claim 5, wherein said first circuit comprises a row predecoder.

8. The circuit according to claim 5, further comprising a control means for second circuit, wherein said second circuit operates in a selected one of a first operating mode, wherein a writing operation is enabled and a reading operation is disabled;

a second operating mode, wherein said writing operation is enabled and said reading operation is enabled; and

a third operating mode, wherein said writing operation is disabled and said reading operation is enabled.

9. A deinterleaving circuit for processing of a signal having blocks of interleaved data packets represented therein, comprising:

a non-interleaved random access memory for memorizing said interleaved packets;

a first circuit for generating an address signal representing a sequence of addresses of said random access memory, wherein successive addresses differ by an addressing interval;

a second circuit for successively reading and writing data out of and into said random access memory respectively at a reading address and a writing address of said random access memory, said reading address and said writing address being determined by said address signal, wherein said address signal is constant during an operation comprising reading and writing data at said address;

a control means for second circuit, wherein said second circuit operates in a selected one of a first operating mode, wherein a writing operation is enabled and a reading operation is disabled;

a second operating mode, wherein said writing operation is enabled and said reading operation is enabled; and

a third operating mode, wherein said writing operation is disabled and said reading operation is enabled; and

a third circuit responsive to a signal ACCEPT BLOCK for periodically increasing said addressing interval by a value equal to an interleaving depth of said interleaved packets wherein said signal ACCEPT BLOCK is asserted after completion of an operation comprising a complete deinterleaving of one of said blocks of data,

wherein said random access memory, said first circuit, said second circuit said third circuit, and said control means are integrated in a semiconductor integrated circuit.