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Signal processing apparatus and method

  • US 5,761,210 A
  • Filed: 06/07/1995
  • Issued: 06/02/1998
  • Est. Priority Date: 06/07/1995
  • Status: Expired due to Term
First Claim
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1. A deinterleaving circuit for processing of a signal comprising blocks of interleaved data packets represented therein, comprising:

  • a random access memory for memorizing a data stream of said blocks of interleaved packets, wherein a capacity of said memory does not exceed any of said blocks;

    a first circuit for generating an address signal representing a sequence of addresses of said random access memory, wherein successive addresses differ by an addressing interval;

    a second circuit for successively reading and writing data out of and into said random access memory respectively at a reading address and a writing address of said random access memory, said reading address and said writing address being determined by said address signal, wherein said address signal is constant during an operation comprising reading and writing data at said address; and

    a third circuit responsive to a signal ACCEPT BLOCK for periodically increasing said addressing interval by a value equal to an interleaving depth of said interleaved packets wherein said signal ACCEPT BLOCK is asserted after completion of an operation comprising a complete deinterleaving of one of said blocks of data.

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