Data integrity guarantee system

• US 5,761,405 A
• Filed: 03/20/1995
• Issued: 06/02/1998
• Est. Priority Date: 12/19/1990
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Okada, Masakazu, Yamaguchi, Syoji, Tadamura, Katsumi
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): VALES, PHILLIP
• Application Number:
  US08/407,241
• Time in Patent Office: 1,170 Days
• Field of Search: 395/182.08, 395/182.09, 395/182.11, 395/182.12, 395/182.14, 395/182.16, 395/182.15, 395/182.02, 395/182.17, 395/182.18, 395/182.19, 370/216-228
• US Class Current: 714/18
• CPC Class Codes: G06F 11/1443 Transmit or communication errors
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 11/2007 using redundant communication media

Abstract

The main storage, the communication interface portion and the circuit control module hold transmission data in the buffers until completion of the transmission has been confirmed. When a fault has occurred in the current operating system of the duplexed portions in the configuration elements of the host computer and the multi-circuit control unit, the duplexed portions are changed over from the current operating system to the stand-by system. In this case, information for reproducing data that has been lost due to the change-over is transmitted from the main storage and the circuit control module to the communication interface portion which has become the new current operating system. The communication interface portion which has become the new current operating system restarts the processing based on this information. Data integrity is guaranteed for the data of both directions of transmission and receiving between the host computer and the terminal without mutually confirming the state of data communications before the occurrence of the fault between the terminal and the host computer after the occurrence of the fault. Information exchanges of layer 3 or above are not carried out between the host computer and the terminal. Therefore, overhead of data communications can be minimized.

Claims

1. A data integrity guarantee system for a communication system in which data packets are sent from a processor to a terminal unit via an active one of a pair of redundant communication interface portions and one of a plurality of circuit control modules and vice versa, herein said processor, said communication interface portions and said circuit control modules each contain a communication buffer for storing transmission data packets and a data communication management table having an indicator for indicating a packet number of the transmitted data packet, and an indicator for indicating a confirmation packet number which is set when a terminal unit has confirmed receipt of a corresponding data packet to a respective transmitting unit, wherein said data integrity system performs the steps of:

(a) storing data packets received from a respective sending unit in a communication buffer of a corresponding receiving unit;

(b) storing, when a data packet is sent out by said processor a packet number of said data packet in said data communication management table in said processor;

(c) storing, upon receipt in an active communication interface portion, said data packet in the communication buffer and storing in said data communication management table a packet number in the corresponding location;

(d) repeating steps (b) and (c) so as to transfer said data packet from said active communication interface portion to a communication buffer of one of said circuit control modules;

(d1) transferring the data packets from a circuit communication module to a terminal unit, which sends back a confirmation signal;

(d2) in response to said confirmation signal, updating packet numbers in said data communication management table of said circuit communication module;

(d3) releasing an area in said communication buffer in said circuit communication module containing the transmitted data packets;

(d4) passing on said confirmation signal to said communication interface portion which updates its packet numbers and releases corresponding areas in said communication buffer;

(d5) sending said confirmation signal to said processor which also updates its packet numbers and releases corresponding areas in said communication buffer;

(d6) performing steps (a) through (d5) for data packet transmission in the other direction from one of the circuit control modules to said active communication interface portion and from said active communication interface portion to said processor, where separate entries for the receiving packet numbers and the receiving confirmation packet numbers are provided in each data communication management table for this direction of data packet transmission;

(d7) when an abnormal state occurs in said active communication interface portion, interrupting data transmission in both directions;

(e) transferring data of said data communication management tables in said processor and in all circuit control modules to a data communication management table of a stand-by communication interface portion;

(f) determining, by comparing packet numbers and confirmation indicators in the various entries of said data communication management tables, whether the data packets sent by said processor have arrived at a circuit control module and vice versa;

(g) retransmitting, if a data packet has not arrived because it was in the communication buffer of an active communication interface portion when the abnormal state occurred, the data packet from the communication buffer of the sending unit and the packet numbers in the data communication management table of said stand-by communication interface portion are updated; and

(h) when all entries in said data communication management table of said stand-by communication interface portion match with the corresponding entries in the data communication management tables of the processor and said circuit control modules, resuming transmission of the data packet and causing said stand-by communication interface portion to become said active communication interface portion.

2. A data integrity guarantee system according to claim 1, wherein each of said processor, said circuit control module and communication interface portion comprises:

means for detecting the number of data packets stored in the corresponding communication buffer; and

means for storing the total number of data packets received by adding a serial number to each data packet.

3. A data integrity guarantee system according to claim 1, wherein said communication interface portion comprises:

means for notifying said circuit control module that restarting of communications is being prepared when the current operating communication interface portion has been changed over to the stand-by communication interface portion; and

means for notifying said circuit control module that it has become possible to transmit to said communication interface portion when it has become possible to restart communications after the current operating communication interface portion was changed over to the stand-by communication interface portion.

4. A data integrity guarantee system according to claim 2, wherein said communication interface portion comprises:

means for notifying said circuit control module that restarting of communications is being prepared when the current operating communication interface portion has been changed over to the stand-by communication interface portion; and

means for notifying said circuit control module that it has become possible to transmit to said communication interface portion when it has become possible to restart communications after the current operating communication interface portion was changed over to the stand-by communication interface portion.

5. A data integrity guarantee system according to claim 1, wherein confirmation signals are transmitted for each data packet separately.

6. A data integrity guarantee system according to claim 2, wherein confirmation signals are transmitted for each data packet separately.

7. A data integrity guarantee system according to claim 3, wherein confirmation signals are transmitted for each data packet separately.

8. A data integrity guarantee system according to claim 4, wherein confirmation signals are transmitted for each data packet separately.

9. A data integrity guarantee system according to claim 1, wherein said processor comprises:

means for transmitting the same data to a plurality of circuits;

wherein each of said processor and said communication interface portion comprises;

a buffer area for multi-cast,

means for storing destinations of a multi-cast transmission, and

means for holding in said buffer area transmission data for the multi-cast transmission until the notice of confirmation of data transmission has been received from all the destinations; and

wherein said circuit control module comprises;

means for discriminating whether the transmission data received from said communication interface is based on a multi-cast transmission or a one-to-one transmission and storing the result.

10. A data integrity guarantee system according to claim 2, wherein said processor comprises:

means for transmitting the same data to a plurality of circuits; and

wherein each of said processor and said communication interface portion comprises;

a buffer area for multi-cast,

means for storing destinations of a multi-cast transmission, and

means for holding in said buffer area transmission data for the multi-cast transmission until the notice of confirmation of data transmission has been received from all the destinations; and

wherein said circuit control module comprises;

means for discriminating whether the transmission data received from said communication interface is based on a multi-cast transmission or a one-to-one transmission and storing the result.

11. A data integrity guarantee system according to claim 3, wherein said processor comprises:

means for transmitting the same data to a plurality of circuits;

wherein each of said processor and said communication interface portion comprises;

a buffer area for multi-cast,

means for storing destinations of a multi-cast transmission, and

means for holding in said buffer area transmission data for the multi-cast transmission until the notice of confirmation of data transmission has been received from all the destinations; and

wherein said circuit control module comprises;

means for discriminating whether the transmission data received from said communication interface is based on a multi-cast transmission or a one-to-one transmission and storing the result.

12. A data integrity guarantee system according to claim 4, wherein said processor comprises:

means for transmitting the same data to a plurality of circuits;

wherein each of said processor and said communication interface portion comprises;

a buffer area for multi-cast,

means for storing destinations of a multi-cast transmission, and

means for holding in said buffer area transmission data for the multi-cast transmission until the notice of confirmation of data transmission has been received from all the destinations; and

wherein said circuit control module comprises;

means for discriminating whether the transmission data received from said communication interface is based on a multi-cast transmission or a one-to-one transmission and storing the result.

13. A data integrity guarantee system according to claim 5, wherein said processor comprises:

means for transmitting the same data to a plurality of circuits;

wherein each of said processor and said communication interface portion comprises;

a buffer area for multi-cast,

means for storing destinations of a multi-cast transmission, and

means for holding in said buffer area transmission data for the multi-cast transmission until the notice of confirmation of data transmission has been received from all the destinations; and

wherein said circuit control module comprises;

means for discriminating whether the transmission data received from said communication interface is based on a multi-cast transmission or a one-to-one transmission and storing the result.

14. A data integrity guarantee system according to claim 1, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

15. A data integrity guarantee system according to claim 2, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

16. A data integrity guarantee system according to claim 3, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

17. A data integrity guarantee system according to claim 4, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

18. A data integrity guarantee system according to claim 5, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

19. A data integrity guarantee system according to claim 6, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

20. A data integrity guarantee system according to claim 7, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

21. A data integrity guarantee system according to claim 8, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

22. A data integrity guarantee system according to claim 9, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

23. A data integrity guarantee system according to claim 10, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

24. A data integrity guarantee system according to claim 11, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

25. A data integrity guarantee system according to claim 12, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

26. A data integrity guarantee system according to claim 13, wherein each communication interface portion comprises:

means for dividing transmission data transmitted from said processor into each said data packet;

means for allocating a sequential number to each divided packet;

means for storing a data name of said transmission data transmitted from said processor and a sequential number of said divided sequential number by corresponding said data name with said sequential number; and

means for collecting said confirmation signal received for each said data packet from said circuit control module, in said transmission data transmitted from said processor.

27. A method of guaranteeing data integrity for a communication system in which data packets are sent from a processor to a terminal unit via an active one of a pair of redundant communication interface portions and one of a plurality of circuit control modules and vice versa, wherein said processor, said communication interface portions and said circuit control modules each contain a communication buffer for storing transmission data packets and a data communication management table comprising an indicator for indicating a packet number of the transmitted data packet, and an indicator for indicating a confirmation packet number which is set when the terminal unit has confirmed the receipt of the corresponding data packet to the respective transmitting unit, said method comprising the steps of:

(a) storing data packets received from a respective sending unit in a communication buffer of a corresponding receiving unit;

(b) storing, when a data packet is sent out by said processor a packet number of said data packet in said data communication management table in said processor;

(c) storing, upon receipt in an active communication interface portion, said data packet in the communication buffer and storing in said data communication management table a packet number in the corresponding location;

(d) repeating steps (b) and (c) so as to transfer said data packet from said active communication interface portion to a communication buffer of one of said circuit control modules;

(d1) transferring the data packets from a circuit communication module to a terminal unit, which sends back a confirmation signal;

(d2) in response to said confirmation signal, updating packet numbers in said data communication management table of said circuit communication module;

(d3) releasing an area in said communication buffer in said circuit communication module containing the transmitted data packets;

(d4) passing on said confirmation signal to said communication interface portion which updates its packet numbers and releases corresponding areas in said communication buffer;

(d5) sending said confirmation signal to said processor which also updates its packet numbers and releases corresponding areas in said communication buffer;

(d6) performing steps (a) through (d5) for data packet transmission in the other direction from one of the circuit control modules to said active communication interface portion and from said active communication interface portion to said processor, where separate entries for the receiving packet numbers and the receiving confirmation packet numbers are provided in each data communication management table for this direction of data packet transmission;

(d7) when an abnormal state occurs in said active communication interface portion, interrupting data transmission in both directions;

(e) transferring data of said data communication management tables in said processor and in all circuit control modules to a data communication management table of a stand-by communication interface portion;

(f) determining, by comparing packet numbers and confirmation indicators in the various entries of said data communication management tables, whether the data packets sent by said processor have arrived at a circuit control module and vice versa;

(g) retransmitting, if a data packet has not arrived because it was in the communication buffer of an active communication interface portion when the abnormal state occurred, the data packet from the communication buffer of the sending unit and the packet numbers in the data communication management table of said stand-by communication interface portion are updated; and

(h) when all entries in said data communication management table of said stand-by communication interface portion match with the corresponding entries in the data communication management tables of the processor and said circuit control modules, resuming transmission of the data packet and causing said stand-by communication interface portion to become said active communication interface portion.

28. A method of guaranteeing data integrity according to claim 27, wherein transmission confirmation signals are transmitted for each data packet separately.

29. A method of guaranteeing data integrity according to claim 27, further comprising the steps of:

detecting the number of data packets of said transmission data to be transmitted to said circuit control module and storing the accumulated number of data packets for each circuit as first information in the corresponding unit; and

detecting the number of data packets of said transmission data to be transmitted to said terminal unit and storing the accumulated number of data packets for each circuit as second information in said communication interface portion, wherein said state of storage is said first information and second information.

30. A method of guaranteeing data integrity according to claim 28, further comprising the steps of:

detecting the number of data packets of said transmission data to be transmitted to said circuit control module and storing the accumulated number of data packets for each circuit as first information in the corresponding unit; and

detecting the number of data packets of said transmission data to be transmitted to said terminal unit and storing the accumulated number of data packets for each circuit as second information in said communication interface portion, wherein said state of storage is said first information and second information.

31. A method of guaranteeing data integrity according to claim 27, further comprising the steps of:

storing a plurality of destinations of each of said transmission data for a multi-cast transmission, in the processor and circuit control modules;

holding said transmission data for said multi-cast transmission in the corresponding communication buffer until transmission to all of said destinations has been confirmed; and

storing said transmission data for said multi-cast transmission in said third memory separate from said transmission data according to one-to-one transmission.

32. A method of guaranteeing data integrity according to claim 28, further comprising the steps of:

storing a plurality of destinations of each of said transmission data for a multi-cast transmission, in the processor and circuit control modules;

holding said transmission data for said multi-cast transmission in the corresponding communication buffer until transmission to all of said destinations has been confirmed; and

storing said transmission data for said multi-cast transmission in said third memory separate from said transmission data according to one-to-one transmission.

33. A method of guaranteeing data integrity according to claim 29, further comprising the steps of:

storing a plurality of destinations of each of said transmission data for a multi-cast transmission, in the processor and circuit control modules;

holding said transmission data for said multi-cast transmission in the corresponding communication buffer until transmission to all of said destinations has been confirmed; and

storing said transmission data for said multi-cast transmission in said third memory separate from said transmission data according to one-to-one transmission.

34. A method of guaranteeing data integrity according to claim 30, further comprising the steps of:

storing a plurality of destinations of each of said transmission data for a multi-cast transmission, in the processor and circuit control modules;

holding said transmission data for said multi-cast transmission in the corresponding communication buffer until transmission to all of said destinations has been confirmed; and

storing said transmission data for said multi-cast transmission in said third memory separate from said transmission data according to one-to-one transmission.