Fault containment system for multiprocessor with shared memory

• US 5,761,413 A
• Filed: 06/05/1995
• Issued: 06/02/1998
• Est. Priority Date: 12/22/1987
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Mann, William F., Frank, Steven J.
• Primary Examiner(s): Decady, Albert
• Application Number:
  US08/462,759
• Time in Patent Office: 1,093 Days
• Field of Search: 371/11, 371/12, 395/575, 395/725, 395/325, 395/185.01, 395/185.02, 395/185.07, 395/185.09, 370/217, 370/553, 370/356, 348/466
• US Class Current: 714/49
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/272 Cache only memory architecture [COMA]
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3865 using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/468 Specific access rights for resources, e.g. using capability register
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: H04L 12/4637 Interconnected ring systems
• CPC Class Codes: H04L 2012/562 Routing
• CPC Class Codes: H04L 45/04 Interdomain routing, e.g. hierarchical routing

Abstract

A multiprocessor system has a plurality of processing cells, each including a processor and memory, interconnected via a network. The memories respond to requests by the processors for accessing data and, absent fault, transmitting it in response packets to at least to the requesting processors. A fault containment element responds to at least certain faults during access or transmission of a datum for including within the respective response packet a fault signal that prevents the requestor from accessing the datum. If a fault is detected in a datum not previously detected as faulty, a marking element can include a "marked fault" signal in the response packet. Whereas, it can include an "unmarked fault" signal when it detects a fault associated with a requested datum, but not specifically isolated to that datum. When a request is made for a datum which had previously been detected as faulty, the marking element can include in the response packet a "descriptor fault" signal. This facilitates identification of a particular source of an error and prevents that error from propagating to other processing cells.

Claims

1. In a digital data processing apparatus of the type having

a plurality of processor means for processing data, each processing unit including request means for generating a request signal representative of a request for access to a datum and for transmitting that request signal on a network means, a processor means generating such a request signal being referred to as a requestor,

at least one memory means for storing data,

said network means being coupled to said processor means and said memory means for transferring signals therebetween,

the improvement wherein

A. said memory means includes response means for responding to at least a selected request signal for accessing the requested datum and, absent fault, transmitting a response signal including that datum on the network means at least to the requestor,

B. said response means includes fault containment means for responding to a fault in connection with at least one of accessing and transmitting the requested datum for generating said response signal to include a fault signal for preventing access by at least said requester to that datum.

2. In a digital data processing apparatus according to claim 1, the further improvement wherein said fault containment means includes fault detection means for detecting a fault in connection with at least one of the accessing and transmitting of said requested datum, said fault detection means including at least one of:

A. marked fault means for responding to a newly detected fault isolated to the requested datum for generating said response signal to include fault signal representative of a fault in a first fault category,

B. unmarked fault means for responding to a fault that is not isolated to the requested datum for generating said response signal to include a fault signal representative of a fault in a second fault category,

C. descriptor fault means for responding to a request for a datum for which a fault had previously been detected for generating said response signal to include a fault signal representative of a fault in a third fault category,

D. local fault means for responding to a fault by the associated memory means in transmitting said response signal on said network means for generating said response signal to include a fault signal representative of a fault in a fourth fault category, and

E. remote fault means for responding to a fault signaled by said network means for generating said response signal to include a fault signal representative of a fault in a fifth fault category.

3. In a digital data processing apparatus according to claim 2, the further improvement wherein

A. at least one processor means other than said requester includes

i) means for storing a status relating to a datum, and

ii) means for normally processing at least selected ones of said response signals by at least updating said status, and

B. said fault containment means includes means for disabling that other processing means from processing a response signal that includes said fault signal.

4. In a digital data processing apparatus according to claim 2, the further improvement wherein

A. each of at least one processor means is associated with a respective one of said memory means, said processor means and associated memory being referred to as a processing cell,

B. said processing cell includes subcache means coupled to the associated processor means for storing data for processing thereby,

C. said memory means includes

i) cache memory means for storing data,

ii) control means coupled to said subcache means and said cache memory means for accessing, absent fault, in said cache memory means at least selected data requested by the associated central processing unit,

D. said control means includes subcache disable means for responding to at least selected faults in operation of at least one of said subcache means and said cache memory means for preventing the transfer of data therebetween.

5. In a digital data processing apparatus as in any one of claims 1, 2, 3, 4, the further improvement wherein at least one of said requester and responder include means responsive to said fault signal for initiating analysis of said fault.

6. In a digital data processing apparatus as in any one of claims 1, 2, 3, 4, the further improvement wherein

A. each of at least selected ones of said data are associated with a descriptor signal by which that data is referenced, and

B. said memory means further includes means for modifying, in the event of selected fault, the descriptor associated with a requested datum to reflect such fault.

7. A digital data processing apparatus comprising

A. one or more processor means for generating requests for access to data stored in a plurality of memory means, each said memory means for storing data,

B. at least a responding one of which memory means comprises means responsive to a selected request for accessing the requested datum in that memory means and for generating a digital signal response packet inclusive thereof,

C. network means coupled to said plural memory means for transferring said digital signal packet therebetween,

D. at least a target one of which memory means includes means normally responsive to a selected response packet for storing the datum contained therein,

E. fault-detection means coupled to said memory means and to said network means for detecting at least a selected fault in connection with the access of said datum and the transfer thereof in said digital signal packet, and

F. said fault-detection means including marking means responsive to such fault condition for including in that digital packet a signal representative thereof.

8. A digital data processing apparatus according to claim 7, wherein

A. said fault-detection means includes means for detecting a selected fault condition isolated to a datum not previously detected as faulty,

said marking means includes means responsive to that fault condition for including in the packet transferring that datum a marked fault signal representative thereof,

B. said fault-detection means includes means for detecting a selected fault condition relating to a datum not previously detected as faulty, which fault is not isolated to that datum, and

said marking means includes means responsive to that fault condition for including in the packet transferring that datum an unmarked fault signal representative thereof.

9. A digital data processing apparatus according to claim 8, wherein

A. said fault-detection means includes means for detecting a request for access to a datum previously detected as faulty, and

B. said marking means includes means responsive to such detection for including, in the packet transferring that datum, a descriptor fault signal indicating that the request was made to a datum previously detected as faulty.

10. A digital data processing apparatus according to claim 7, wherein

A. at least said responding memory means includes directory means for storing a fault flag, associated with a corresponding datum, which fault flag is not set in the absence of fault in that datum, is not set, and

B. said fault-detection means includes means for detecting a selected fault condition isolated to a datum not previously detected as faulty,

said marking means includes means responsive to that fault condition for setting the fault flag corresponding to that datum

C. said fault-detection means includes means for detecting a request for access to a datum for which the corresponding fault flag is set, and

said marking means includes means responsive to that detection for including in the packet transferring that datum a descriptor fault signal indicating that the request was made for a datum previously detected as faulty.

11. A digital data processing apparatus according to claim 7, wherein

A. said network means includes bus means including

i) a plurality of segment means each for carrying said digital signal packets, and

ii) routing means coupled to respective pairs of said segment means for selectively transferring digital signal packets therebetween,

B. said fault-detection means includes means for detecting a fault in the transfer of a digital signal packet by said routing means, and

C. said marking means includes means responsive to that fault condition for including in that digital signal packet a remote fault signal representative thereof.

12. A digital data processing apparatus according to claim 11, wherein

A. said network means includes (i) bus means for carrying said packets, and (ii) a plurality of control means, each coupled to a respective one of said memory means and to said bus means, for selectively transferring said packets therebetween,

B. said fault-detection means includes means for detecting a fault in the transfer of a digital signal packet by said control means, and

C. said marking means includes means responsive to that fault condition for including in that digital signal packet a local fault signal representative thereof.

13. A digital data processing apparatus as in any one of claims 8, 9, 11, 10, 12, wherein said target memory means comprises means responsive to a selected response packet including said fault signal for preventing storage in that memory means of the datum contained in that response packet.

14. A digital data processing apparatus as in any one of claims 8, 9, 11, 10, 12, wherein at least one memory means other than said responding memory means comprises

A. means for storing a status relating to a datum in a response packet,

B. means for normally updating that status in response to transfer of a response packet containing that datum, and

C. means responsive to said fault signal in a packet containing that datum for preventing updating of that status.

15. A digital data processing apparatus as in any one of claims 8, 9, 11, 10, 12, wherein

A. at least one said processor means is associated with a respective one of said memory means, said processor means and associated memory being referred to as a processing cell,

B. said processing cell including subcache means coupled to the associated processor means for storing data for processing thereby,

C. said memory means includes

i) cache memory means for storing data,

ii) control means coupled to said subcache means and said cache memory means for accessing, absent fault, in said cache memory means at least selected data requested by the associated central processing unit,

D. said control means includes subcache disable means for responding to at least selected faults in operation of at least one of said subcache means and said cache memory means for preventing the transfer of data therebetween.

16. A digital data processing apparatus as in any one of claims 7, 8, 9, 11, 10, 12, wherein

A. each said datum is associated with an address by which that datum is referenced, and wherein the addresses associated with the data stored in said plurality of memory elements comprise a single virtual address space,

B. said one or more processor means include means for generating said request for access specifying the address associated with the requested datum, and

C. at least said responding memory means includes means selectively responsive to said specified address for accessing the requested datum therein.

17. A digital data processing apparatus as in any one of claims 7, 8, 9, 11, 10, 12, wherein at least one of said memory means includes responsive to said fault signal for initiating analysis of said fault.

18. A digital data processing apparatus as in any one of claims 7, 8, 9, 11, 10, 12, wherein at least said responding memory means includes

A. directory means for storing a fault flag, associated with a corresponding datum, which fault flag is not set in the absence of fault in that datum, and

B. said fault-detection means includes means responsive to at least a selected fault condition associated with that datum for setting that fault flag.

19. A method of operating a digital data processing apparatus of the type having

a plurality of processor means for processing data, each processing unit including request means for generating a request signal representative of a request for access to a datum and for transmitting that request signal on a network means, a processor means generating such a request signal being referred to as a requestor,

at least one memory means for storing data,

said network means being coupled to said processor means and said memory means for transferring signals therebetween,

the method comprising the steps of

A. responding to at least a selected request signal for accessing the requested datum in said memory means and, absent fault, transmitting a response signal including that datum on the network means at least to the requester,

B. responding to a fault in connection with at least one of accessing and transmitting the requested datum for generating said response signal to include a fault signal for preventing access by at least said requester to that datum.

20. A method according to claim 19, comprising the steps of

A. detecting a fault in connection with at least one of the accessing and transmitting of said requested datum, and

B. selectively executing, in response to such detection, at least one of the following steps

i) responding to a newly detected fault isolated to the requested datum for generating said response signal to include fault signal representative of a fault in a first fault category,

ii) responding to a fault that is not isolated to the requested datum for generating said response signal to include a fault signal representative of a fault in a second fault category,

iii) responding to a request for a datum for which a fault had previously been detected for generating said response signal to include a fault signal representative of a fault in a third fault category,

iv) responding to a fault by the associated memory means in transmitting said response signal on said network means for generating said response signal to include a fault signal representative of a fault in a fourth fault category, and

v) responding to a fault signaled by said network means for generating said response signal to include a fault signal representative of a fault in a fifth fault category.

21. A method according to claim 20, comprising the steps of

A. storing, within at least one memory means other than said requestor, a status relating to a datum, and normally responding to at least selected ones of said response signals for updating said status, and

B. disabling that other processing cell from processing a response signal that includes said fault signal.

22. A method according to claim 20, wherein each of at least one processor means is associated with a respective one of said memory means, said processor means and associated memory being referred to as a processing cell, said method comprising the steps of

A. providing said processing cell with subcache means coupled to the associated processor means for storing data for processed thereby,

B. providing said memory means with cache memory means for storing data, and control means coupled to said subcache means and said cache memory means for accessing absent fault, in said cache memory means at least selected data requested by the associated central processing unit, and

C. responding to at least selected faults in operation of at least one of said subcache means and said cache memory means for preventing the transfer of data therebetween.

23. A method as in any one of claims 19, 20, 21, 22, comprising the step of responding to said fault signal for initiating analysis of said fault.

24. A method as in any one of claims 19, 20, 21, 22, wherein each of at least selected ones of said data are associated with a descriptor signal by which that datum is referenced, said method comprising the step of modifying, in the event of selected fault, the descriptor associated with a requested datum to reflect such fault.

25. A method of operation a digital data processing apparatus comprising

A. providing one or more processor means for generating requests for access to data stored in a plurality of memory means, each said memory means for storing data,

B. responding to a selected request for accessing a requested datum in a memory means and generating a digital signal response packet inclusive of that datum,

C. transferring said digital signal packet between said plural memory means,

D. normally responding to a selected response packet for storing the datum contained therein in another memory means,

E. detecting at least a selected fault in connection with the access of said datum and the transfer thereof in said digital signal packet, and

F. responding to such fault condition for including in that digital packet a signal representative thereof.

26. A method according to claim 25, comprising

A. detecting a selected fault condition isolated to a datum not previously detected as faulty,

responding to that fault condition for including in the packet transferring that datum a marked fault signal representative thereof,

B. detecting a selected fault condition relating to a datum not previously detected as faulty, which fault is not isolated to that datum, and

responding to that fault condition for including in the packet transferring that datum an unmarked fault signal representative thereof.

27. A method according to claim 26, comprising

A. detecting a request for access to a datum previously detected as faulty, and

B. responding to such detection for including, in the packet transferring that datum, a descriptor fault signal indicating that the request was made to a datum previously detected as faulty.

28. A method according to claim 25, comprising

A. storing a fault flag, associated with a corresponding datum, which fault flag is not set in the absence of fault in that datum,

B. detecting a selected fault condition isolated to a datum not previously detected as faulty, responding to that fault condition for setting the fault flag corresponding to that datum

C. detecting a request for access to a datum for which the corresponding fault flag is set, and responding to that detection for including in the packet transferring that datum a descriptor fault signal indicating that the request was made for a datum previously detected as faulty.

29. A method according to claim 25, comprising

A. providing a bus means including a plurality of segment means each for carrying said digital signal packets, and routing means coupled to respective pairs of said segment means for selectively transferring digital signal packets therebetween,

B. detecting a fault in the transfer of a digital signal packet by said routing means, and

C. responding to that fault condition for including in that digital signal packet a remote fault signal representative thereof.

30. A method according to claim 29, comprising

A. providing said network means with (i) bus means for carrying said packets, and (ii) a plurality of control means, each coupled to a respective one of said memory means and to said bus means, for selectively transferring said packets therebetween,

B. detecting a fault in the transfer of a digital signal packet by said control means, and

C. responding to that fault condition for including in that digital signal packet a local fault signal representative thereof.

31. A method as in any one of claims 26, 27, 29, 28, 30, comprising responding to a selected response packet including said fault signal for preventing storage in that memory means of the datum contained in that response packet.

32. A method as in any one of claims 26, 27, 29, 28, 30, comprising

A. storing a status relating to a datum in a response packet,

B. normally updating that status in response to transfer of a response packet containing that datum, and

C. responding to said fault signal in a packet containing that datum for preventing updating of that status.

33. A method as in any one of claims 25, 26, 27, 29, 28, 30, wherein each said datum is associated with an address by which that datum is referenced, and wherein the addresses associated with the data stored in said plurality of memory elements comprise a single virtual address space, comprising the steps of

A. generating said request for access specifying the address associated with the requested datum, and

B. selectively responding to said specified address for accessing the requested datum therein.

34. A method as in any one of claims 25, 26, 27, 29, 28, 30, comprising responding to said fault signal for initiating analysis of said fault.

35. A method as in any one of claims 25, 26, 27, 29, 28, 30, comprising

A. storing a fault flag, associated with a corresponding datum, which fault flag is not set in the absence of fault in that datum, and

B. responding to at least a selected fault condition associated with that datum for setting that fault flag.