Processor device having automatic bus sizing

• US 5,761,456 A
• Filed: 04/03/1996
• Issued: 06/02/1998
• Est. Priority Date: 04/03/1996
• Status: Expired due to Term

• Current Assignee: Trimble Navigation Limited (Trimble Inc.)
• Original Assignee: Trimble Navigation Limited (Trimble Inc.)
• Inventors: Will, Stephen K., Titus, Scott Duane, Martin, Kreg A.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): THLANG, ERIC S
• Application Number:
  US08/627,952
• Time in Patent Office: 790 Days
• Field of Search: 395/307, 395/325, 395/500, 395/183.21, 395/292, 395/280, 395/829, 364/578, 364/443, 364/579, 364/489, 342/357
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4217 with synchronous protocol

Abstract

A processor device and method for booting a programmable apparatus having a signal bus having a selectable bus width. The processor device includes a microprocessor, a configurable bus interface for coupling the microprocessor to the signal bus, and a first memory. The first memory includes a bus sizing code for instructing the microprocessor for reading initial data from a pre-determined address of a second memory and configuring the bus interface to the bus width that has been selected. The first memory further includes a checksum code for a self-test of the memory, an emulator detect code for skipping the checksum code when control of the microprocessor is transferred to an emulator, a delay code for delaying a start of operation of the programmable apparatus when circuits in the programmable apparatus have a restrictive voltage requirement, and a monitor request code for transferring control to a monitor code when requested by an external user or when a self-test fails.

Claims

1. A processor for use in booting a programmable apparatus having a signal bus and an apparatus memory coupled to said signal bus, comprising:

a bus interface for connection to said signal bus;

a microprocessor coupled to the bus interface; and

a processor memory coupled to the microprocessor, including a code for instructing the microprocessor for reading said apparatus memory including an emulator flag for indicating when said apparatus memory is replaced by an emulator, said emulator including an emulator code; and

further including an emulator detect code for instructing the microprocessor for transferring control to said emulator code when said emulator flag indicates that said apparatus memory is replaced by said emulator.

2. The processor of claim 1, wherein:

the processor memory further includes a checksum code for instructing said microprocessor for performing a checksum test of said apparatus memory and for skipping said checksum test when said emulator flag indicates that said apparatus memory is replaced by said emulator.

3. A processor for use in booting a programmable apparatus having a delay flag, a signal bus and an apparatus memory coupled to said signal bus, comprising:

a bus interface for connection to said signal bus;

a microprocessor coupled to the bus interface and said delay flag;

a processor memory, coupled to the microprocessor, for instructing the microprocessor for reading from said apparatus memory including an application program code; and

the processor memory including a delay code for instructing the microprocessor for reading said delay flag and for delaying a transfer of control of the microprocessor to said application program code when said delay flag is asserted.

4. A processor for use in booting a programmable apparatus having a monitor flag, a signal bus and an apparatus memory coupled to the signal bus comprising:

a bus interface for connection to said signal bus,

a microprocessor coupled to the bus interface and said monitor flag;

a processor memory, coupled to the microprocessor, for instructing the microprocessor for reading from said apparatus memory including a monitor code for enabling a user to read from said apparatus memory; and

the processor memory including a monitor request code for instructing the microprocessor for transferring control of the microprocessor to said monitor code when said monitor flag is asserted.

5. A processor, for use in booting a programmable apparatus having a signal bus and an apparatus memory coupled to said signal bus, comprising:

a configurable bus interface for connection to said signal bus, said signal bus having a selectable bus width;

a microprocessor coupled to the bus interface; and

a processor memory coupled to the microprocessor, including a bus sizing code for instructing the microprocessor for reading said apparatus memory including initial data for configuring said bus interface to said selectable bus width where said initial data indicates which said selectable bus width has been selected, wherein the bus interface, the microprocessor, and the processor memory are integrated into a single integrated package.

6. A processor for use in booting a global positioning system (GPS) receiver having a signal bus and an apparatus memory coupled to said signal bus, comprising:

a configurable bus interface for connection to said signal bus, said signal bus having a selectable bus width;

a microprocessor coupled to the bus interface; and

a processor memory, coupled to the microprocessor, including a bus sizing code for instructing the microprocessor for reading said apparatus memory including initial data for configuring said bus interface to said selectable bus width where said initial data indicates which said selectable bus width has been selected.

7. A method in a processor for boot-up of a programmable apparatus having an apparatus memory coupled to a signal bus, comprising steps of:

connecting said processor to said signal bus,

providing an emulator for replacing said apparatus memory;

providing an emulator flag;

reading said emulator flag with said processor; and

transferring control of said processor to an emulator code in said apparatus memory when said emulator flag indicates that said apparatus memory is replaced by said emulator.

8. The method of claim 7, further including a step of:

testing said apparatus memory for a checksum when said emulator flag indicates that said apparatus memory is not replaced by an emulator and skipping said testing for said checksum when said emulator flag indicates that said apparatus memory is not replaced by an emulator.

9. A method in a processor for boot-up of a programmable apparatus having a delay flag, a signal bus, and an apparatus memory including initial data having information for said boot up coupled to said signal bus, comprising steps of:

coupling said processor to said signal bus and said delay flag;

reading said delay flag with said processor;

delaying reading of said initial data for completion of said boot-up when said delay flag is asserted; and

reading said initial data with said processor after said delay flag is unasserted.

10. A method in a processor for boot-up of a programmable apparatus having a monitor request flag, a signal bus and an apparatus memory including an application program code and a monitor code coupled to said signal bus, comprising steps of:

coupling said processor to said signal bus and said monitor request flag;

reading said monitor request flag;

transferring control of said processor to said monitor code when said monitor request flag is asserted; and

operating said processor according to said application program code when said monitor request flag is unasserted.

11. A method in a processor for boot-up of a global positioning system (GPS) receiver having an apparatus memory having initial data coupled to a signal bus having a selected one of at least two possible bus widths, comprising steps of:

programming said initial data for indicating said selected bus width;

coupling said processor to said signal bus;

reading said initial data with said processor over said signal bus; and

configuring said processor to said selected bus width based upon said initial data.