Prefetching variable length data

• US 5,761,464 A
• Filed: 05/22/1995
• Issued: 06/02/1998
• Est. Priority Date: 05/22/1995
• Status: Expired due to Term

• Current Assignee: EMC Corporation (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Hopkins, Charles H.
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US08/447,088
• Time in Patent Office: 1,107 Days
• Field of Search: 395/308, 395/310, 395/584, 711/171
• US Class Current: 710/310
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

An interface unit connected between a first bus and a second bus, the first bus having connected thereto a memory system and the second bus having connected thereto a plurality of devices which perform read operations directed at the memory system, the interface unit including a buffer memory having an input that is electrically coupled to the first bus for receiving data that is sent from the memory system over the first bus and an output that is electrically coupled to the second bus for delivering data to the second bus for transfer to a requesting device, the requesting device being one of the plurality of devices; a plurality of prefetch size registers equal in number to the plurality of devices, wherein each of the plurality of prefetch size registers stores a number for a different corresponding one of the plurality of devices, wherein the number stored in each of the plurality of prefetch size registers specifies an amount of data that is prefetched from memory in response to a data read request from the corresponding device; and a control unit which in response to a data read request from any one of the plurality of devices prefetches into the buffer a predetermined amount of data from the system memory, the predetermined amount being determined by the number stored in prefetch size register corresponding to the requesting device.

Claims

1. An interface unit connected between a first bus and a second bus, said first bus having connected thereto a memory system and said second bus having connected thereto a plurality of devices which perform read operations directed at said memory system, said interface unit comprising:

a buffer memory having an input that is electrically coupled to the first bus for receiving data that is sent from said memory system over said first bus and an output that is electrically coupled to said second bus for delivering data to said second bus for transfer to a requesting device, said requesting device being one of said plurality of devices;

a plurality of prefetch size registers equal in number to said plurality of devices, wherein each of said plurality of prefetch size registers stores a number for a different corresponding one of said plurality of devices, wherein the number stored in each of said plurality of prefetch size registers specifies an amount of data that is prefetched from memory in response to a data read request from the corresponding device; and

a control unit which in response to a data read request from any one of said plurality of devices prefetches into said buffer a predetermined amount of data from said system memory, said predetermined amount being determined by the number stored in the prefetch size register corresponding to the requesting device.

2. The interface unit of claim 1 further comprising a prefetch counter register, wherein in response to a data read request from said requesting device said control unit loads said prefetch counter register with the number stored in the prefetch size register corresponding to the requesting device and wherein said control unit uses the contents of said prefetch counter to determine when the predetermined amount of data has been prefetched from said memory system.

3. The interface unit of claim 2 wherein said control unit decrements the contents of said prefetch counter in response to the prefetched data being received by said interface unit over the first bus.

4. The interface unit of claim 3 wherein said control unit comprises an arbiter which arbitrates among data read requests from said plurality of devices to determine which data read request is granted.

5. The interface unit of claim 2 further comprising an address register electrically coupled to the second bus, said address register receiving and storing an address provided by the requesting device, said address identifying the location in the memory system of data.

6. The interface unit of claim 5 wherein the control unit increments the contents of the address register as the prefetched data is being received by said interface unit over the first bus.

7. A method of prefetching data in a system including a first bus to which a memory system is connected and a second bus to which a plurality of devices are connected, said method comprising:

providing a plurality of prefetch size registers equal in number to said plurality of devices, each of said prefetch size registers corresponding to a different one of said devices;

storing a plurality of prefetch amounts in said plurality of prefetch registers, each prefetch amount of said plurality of prefetch amounts being stored in a different corresponding one of said prefetch size registers;

in response to receiving a data read request from one of said plurality of devices, reading the prefetch amount that is stored in the prefetch register which corresponds to the requesting device;

prefetching a predetermined amount of data from said system memory over the first bus, said predetermined amount being equal in size to the prefetch amount for the requesting device;

storing the prefetched data in a buffer; and

transferring the prefetched data from the buffer to the requesting device over the second bus.

8. The method of claim 7 further comprising:

providing a prefetch counter;

in response to receiving said data read request from the requesting device, loading into said prefetch counter the number that is stored in the prefetch size register for the requesting device; and

using the contents of said prefetch counter to establish when prefetched data of a sufficient amount has been prefetched from said system memory.

9. The method of claim 8 wherein the step of using the contents of said prefetch counter to establish the amount of data that is prefetched from said system memory comprises:

as prefetched data is being prefetched from the memory system, decrementing the contents of the prefetch counter; and

when the contents of said prefetch counter equals a preselected number, terminating the prefetching of data from said memory system.

10. The method of claim 8 further comprising:

providing an address register; and

in response to receiving said data read request from the requesting device, loading said address register with an address provided by the requesting device, wherein the step of prefetching data from system memory comprises using the contents of the address register to identify locations of data being prefetched from system memory.

11. The method of claim 10 further comprising incrementing the contents of the address register as data is being prefetched from system memory.

12. The method of claim 7 further comprising:

performing a read operation over the second bus to obtain information about each of said plurality of devices attached to the second bus; and

determining the prefetch amounts for each of said prefetch size registers from the information obtained for each of said plurality of devices.

13. The method of claim 12 further comprising:

providing a table mapping information about each of said plurality of devices to prefetch amounts;

wherein the step of determining the prefetch amounts comprises cross-referencing through said table.

14. The method of claim 13 wherein each of said plurality of devices includes an internal buffer having a predetermined size and wherein the prefetch amounts for each of said devices is equal to the size of the internal buffer for that device.