Optimizing and operating a time multiplexed programmable logic device
First Claim
1. A computer-implemented method of designing a time multiplexed programmable logic device, comprising:
- entering a circuit design for said programmable logic device;
mapping said circuit design to the physical resources of said programmable logic device, wherein said physical resources include configurable logic elements;
determining an appropriate micro cycle for each configurable logic element in said design;
placing said resources on said programmable logic device; and
connecting said resources.
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Abstract
A method of optimizing a time multiplexed programmable logic device (PLD) includes entering a circuit design for the PLD, mapping the design to the physical resources of the PLD (wherein the physical resources include configurable logic elements), determining an appropriate micro cycle for each configurable logic element in the design, placing the resources on the PLD, and connecting the resources. Optimizing the design may include reducing the number of look up tables or reducing the logic depth of the look up tables. If the configurable logic elements include sequential logic elements, then the optimizing step includes rescheduling the sequential logic elements. A method of operating a time multiplexed PLD in a logic engine mode includes programming the PLD to implement a design in stages, wherein each stage is one configuration, sequencing the PLD through all the configurations, and storing the results of the logic performed in one configuration in a plurality of micro registers for use in subsequent configurations. In one embodiment, the PLD includes a plurality of combinational elements and sequential logic elements, wherein the values stored by the sequential logic elements are stored in the micro registers.
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Citations
12 Claims
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1. A computer-implemented method of designing a time multiplexed programmable logic device, comprising:
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entering a circuit design for said programmable logic device; mapping said circuit design to the physical resources of said programmable logic device, wherein said physical resources include configurable logic elements; determining an appropriate micro cycle for each configurable logic element in said design; placing said resources on said programmable logic device; and connecting said resources. - View Dependent Claims (2, 3, 4, 5)
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6. A computer-implemented method of designing a time multiplexed programmable logic device, comprising:
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entering a circuit design for said programmable logic device; mapping said design to the physical resources of said programmable logic device, wherein said physical resources include configurable logic elements; simultaneously determining an appropriate micro cycle for each configurable logic element in said design and placing said resources on said programmable logic device; and connecting said resources.
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7. A method of time multiplexing a programmable logic device comprising:
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scheduling the logic of said programmable logic device to be evaluated in a plurality of micro cycles; and scheduling the logic of a critical path in said programmable logic device to be evaluated in sequential micro cycles.
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8. A computer-implemented method of operating a time multiplexed programmable logic device in a logic engine mode, comprising:
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programming said programmable logic device to implement a design in stages, wherein each stage is one configuration; sequencing said programmable logic device through at least one of the configurations; storing the results of the logic performed in one configuration in a plurality of micro registers for use in subsequent configurations. - View Dependent Claims (9, 10, 11, 12)
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Specification